Re: did the zephyr kernel support the nested interrupt on all the supported arch?


Benjamin Walsh <benjamin.walsh@...>
 

Hi,

i have reviewed the cortex-m arch about the interrupt flow, and
found that cortex-m support max 255 interrupt entry and it
allows interrupt with higher prio preempted another one with
lower priority interrupt,

i did not see other arch`s code but just want to know about, is this
the feature of zephyr kernel? for the strong real-time feature? or
arch related?
Should be supported on architectures where the hardware has support for
it. It is a feature of the kernel.

ARM, ARC, x86 do support it.

Not entirely sure about Nios2 and RiscV.

Regards,
Ben

--
Benjamin Walsh, SMTS
WR VxWorks Virtualization Profile
www.windriver.com
Zephyr kernel maintainer
www.zephyrproject.org

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