Re: Porting to Cortex-M0+

Benjamin Walsh <benjamin.walsh@...>

Hi Euan,

I am in the process of porting Zephyr to Cortex-M0+, the problem is
that for the M0+ if you use a Supervisor Call (SVC) with interrupts
disabled, since there is no interrupt masking either, then the
Supervisor Call will generate a hard fault.

Which means that every time _Swap() is called it hard faults.

Currently I have managed to get round this by just commenting out the
disabling of interrupts before _Swap() is called. However I don't
think this is a viable long term solution!
Indeed, it is not. :)

Do I have to rewrite _Swap() to not use SVC or is there another way to
do it that I have missed?
You have to take another approach in this case. I _think_ you can simply
pend the PendSV exception instead, and then unlock interrupts.

You have to use PRIMASK instead of BASEPRI as well for the interrupt
locking, since there is no BASEPRI on M0 (IIRC). Some of the ARM arch
code has to be adapted to that as well.

The SVC handler for M3/M4 does not do much more work than that anyway
(apart from the IRQ offload). We might be able to merge the M0 and
M3/M4 implementations as well.


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