Re: Porting to Cortex-M0+

Ricardo Salveti <ricardo.salveti@...>

Hi Euan,

On Thu, Aug 4, 2016 at 6:00 AM, Euan Mutch <euan.mutch(a)> wrote:
Hi Ben,

That seems to be working properly now with the interrupts being disabled.

We might be able to merge the M0 and
M3/M4 implementations as well.
I have been trying to make sure that anything I change still works on M3/M4
and will add config options where a common approach would not work.
I was looking at what would take to get Zephyr to support Cortex-M0
today (wanted to port Zephyr to nRF51), and found your thread :-)

Are you expecting to open source/upstream your Cortex M0+ based port?
Wanted to avoid duplicating this effort, as the M0 port would be quite
similar with M0+. Happy to test/review your implementation as well.

Ricardo Salveti

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