Re: How to handle a board with a dozen SoC's?

Boie, Andrew P

On Fri, 2016-09-02 at 15:46 +0100, Jon Medhurst (Tixy) wrote:
I'm trying to add Zephyr support for a board [1] where the 'SoC' is an
FPGA that can be programmed with a dozen different CPU types and
varying support IP, and I'm wondering how to organise this.
I realised this and $subject may be a bit ambiguous, I meant that the FPGA can
be programmed at any one time with a single CPU type chosen from a range of
a dozen or so. I'm not trying to support multiple CPU and 'SoC' types in a single
Zephyr image at the same time. I'm looking at a separate image for each one.

What I did for Nios II (which is a soft-CPU that runs on Altera FPGAs) is to define each different Nios II configuration as a different soc in the Zephyr build.

So for example I have the "nios2f-zephyr" soc which is the reference config. Then another one "nios2-qemu" for the QEMU emulator which has slightly different settings. Each one has a system.h header file with all the configuration details. In this case the system.h was generated by the Altera tools.

See arch/nios2/soc/ for what I mean.
This is assuming that the CPU types you want to support are of a family of the same basic architecture with different configuration options.


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