Re: Has anyone used the USB HS port used as a USB FS on STM32F4?


Aurelien Jarno
 

Hi Yannis,

On 2018-07-10 11:30, Yannis Damigos wrote:
Hi Jun and Aurelien,

I created the following branch in my repository to add support for OTG
HS: https://github.com/ydamigos/zephyr/commits/stm32_otg_hs

It was tested on stm32f429 SoC by Jun and on STM32F723E-DISCO by Aurelien.

I updated my repository following your comments. Could you test it
again because I don't have the hw?
Thanks for this new version, and for working on it blindly without the
hardware.

I have just tested it on the STM32F723E-DISCO board on top PR#8667. I
had to do a few changes:
- The PHY has to be USB_OTG_HS_EMBEDDED_PHY on that board as it doesn't
have an embedded full-speed PHY
- The check on CONFIG_SERIES_STM32F7X is wrong and should be
CONFIG_SOC_SERIES_STM32F7X instead.

I also I believe that the STM32F7 SoCs without embedded HS speed behave
the same than the STM32F4. Therefore I think that both OTGHSULPI and
OTGPHYC clocks should be enabled if the SoC has an internal HS PHY,
otherwise OTGHSULPI should be disabled.

I have added a patch fixing the small issues and doing that changes at
the end of this mail.

Note that right now it's still work on full-speed mode even on this
board, but I think that should be changed later in a second step.

Before opening a PR upstream I would like to add support for the
boards you tested it. Could you open a pull request to my branch?
The support for USB on the board I tested is still not merged, it's
PR#8667. Then enabling it is just about replacing usbotg_fs by usbotg_hs
in stm32f723e_disco.dts. Strangely pinmux changes are not needed. I am
not sure which USB connector we want to enable as default on this board.

Aurelien


diff --git a/drivers/usb/device/usb_dc_stm32.c b/drivers/usb/device/usb_dc_stm32.c
index f11233535..c85bca9a5 100644
--- a/drivers/usb/device/usb_dc_stm32.c
+++ b/drivers/usb/device/usb_dc_stm32.c
@@ -248,17 +248,14 @@ static int usb_dc_stm32_clock_enable(void)

#ifdef CONFIG_USB_HS_BASE_ADDRESS

-#ifdef CONFIG_SERIES_STM32F7X
- LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_OTGHSULPI);
-
#ifdef USB_HS_PHYC
+ /* Enable ULPI interface and internal high-speed PHY clocks */
+ LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_OTGHSULPI);
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_OTGPHYC);
-#endif /* USB_HS_PHYC
-
#else
/* Disable ULPI interface (for external high-speed PHY) clock */
LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_OTGHSULPI);
-#endif /* CONFIG_SERIES_STM32F7X */
+#endif /* USB_HS_PHYC */

#endif /* CONFIG_USB_HS_BASE_ADDRESS */

@@ -285,7 +282,11 @@ static int usb_dc_stm32_init(void)
#endif
usb_dc_stm32_state.pcd.Init.dev_endpoints = CONFIG_USB_NUM_BIDIR_ENDPOINTS;
usb_dc_stm32_state.pcd.Init.speed = USB_OTG_SPEED_FULL;
+#ifdef USB_HS_PHYC
+ usb_dc_stm32_state.pcd.Init.phy_itface = USB_OTG_HS_EMBEDDED_PHY;
+#else
usb_dc_stm32_state.pcd.Init.phy_itface = PCD_PHY_EMBEDDED;
+#endif /* USB_HS_PHYC */
usb_dc_stm32_state.pcd.Init.ep0_mps = USB_OTG_MAX_EP0_SIZE;
usb_dc_stm32_state.pcd.Init.vbus_sensing_enable = DISABLE;



--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurelien@aurel32.net http://www.aurel32.net

Join devel@lists.zephyrproject.org to automatically receive all group messages.