Hi Aurelien,

Thanks for reviewing it.

- The PHY has to be USB_OTG_HS_EMBEDDED_PHY on that board as it doesn't
have an embedded full-speed PHY

Strange. STM32F72xxx SoC reference manual mentions an on-chip full-speed PHY.

- The check on CONFIG_SERIES_STM32F7X is wrong and should be
CONFIG_SOC_SERIES_STM32F7X instead.

Fixed.

I also I believe that the STM32F7 SoCs without embedded HS speed behave
the same than the STM32F4. Therefore I think that both OTGHSULPI and
OTGPHYC clocks should be enabled if the SoC has an internal HS PHY,
otherwise OTGHSULPI should be disabled.

I agree. That's why I am trying to find a way to define the PHYs
(maybe in device tree).

diff --git a/drivers/usb/device/usb_dc_stm32.c b/drivers/usb/device/usb_dc_stm32.c
index f11233535..c85bca9a5 100644
--- a/drivers/usb/device/usb_dc_stm32.c
+++ b/drivers/usb/device/usb_dc_stm32.c
@@ -248,17 +248,14 @@ static int usb_dc_stm32_clock_enable(void)

#ifdef CONFIG_USB_HS_BASE_ADDRESS

-#ifdef CONFIG_SERIES_STM32F7X
- LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_OTGHSULPI);
-
#ifdef USB_HS_PHYC
+ /* Enable ULPI interface and internal high-speed PHY clocks */
+ LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_OTGHSULPI);
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_OTGPHYC);
-#endif /* USB_HS_PHYC
-
#else
/* Disable ULPI interface (for external high-speed PHY) clock */
LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_OTGHSULPI);
-#endif /* CONFIG_SERIES_STM32F7X */
+#endif /* USB_HS_PHYC */

#endif /* CONFIG_USB_HS_BASE_ADDRESS */

USB_HS_PHYC is not defined on all STM32F7 SoCs, so enabling ULPI clock
if it is defined won't
work on other SoCs.

@@ -285,7 +282,11 @@ static int usb_dc_stm32_init(void)
#endif
usb_dc_stm32_state.pcd.Init.dev_endpoints = CONFIG_USB_NUM_BIDIR_ENDPOINTS;
usb_dc_stm32_state.pcd.Init.speed = USB_OTG_SPEED_FULL;
+#ifdef USB_HS_PHYC
+ usb_dc_stm32_state.pcd.Init.phy_itface = USB_OTG_HS_EMBEDDED_PHY;
+#else
usb_dc_stm32_state.pcd.Init.phy_itface = PCD_PHY_EMBEDDED;
+#endif /* USB_HS_PHYC */
usb_dc_stm32_state.pcd.Init.ep0_mps = USB_OTG_MAX_EP0_SIZE;
usb_dc_stm32_state.pcd.Init.vbus_sensing_enable = DISABLE;

The PR is focused on enabling FS mode on OTG_HS that's why I didn't
change PHY interface.

Yannis