Re: Has anyone used the USB HS port used as a USB FS on STM32F4?


Aurelien Jarno
 

On 2018-07-11 11:03, Yannis Damigos wrote:
Hi Aurelien,

Thanks for reviewing it.

- The PHY has to be USB_OTG_HS_EMBEDDED_PHY on that board as it doesn't
have an embedded full-speed PHY
Strange. STM32F72xxx SoC reference manual mentions an on-chip full-speed PHY.
All the STM32F7 SoCs except the STM32F723 have an on-chip FS PHY, just
like the STM32F4 family. The STM32F723 only has an on-chip HS PHY and
does not have the FS PHY.

You can see that on RM0431, pages 1172 and 1173.

- The check on CONFIG_SERIES_STM32F7X is wrong and should be
CONFIG_SOC_SERIES_STM32F7X instead.
Fixed.

I also I believe that the STM32F7 SoCs without embedded HS speed behave
the same than the STM32F4. Therefore I think that both OTGHSULPI and
OTGPHYC clocks should be enabled if the SoC has an internal HS PHY,
otherwise OTGHSULPI should be disabled.
I agree. That's why I am trying to find a way to define the PHYs
(maybe in device tree).

diff --git a/drivers/usb/device/usb_dc_stm32.c b/drivers/usb/device/usb_dc_stm32.c
index f11233535..c85bca9a5 100644
--- a/drivers/usb/device/usb_dc_stm32.c
+++ b/drivers/usb/device/usb_dc_stm32.c
@@ -248,17 +248,14 @@ static int usb_dc_stm32_clock_enable(void)

#ifdef CONFIG_USB_HS_BASE_ADDRESS

-#ifdef CONFIG_SERIES_STM32F7X
- LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_OTGHSULPI);
-
#ifdef USB_HS_PHYC
+ /* Enable ULPI interface and internal high-speed PHY clocks */
+ LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_OTGHSULPI);
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_OTGPHYC);
-#endif /* USB_HS_PHYC
-
#else
/* Disable ULPI interface (for external high-speed PHY) clock */
LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_OTGHSULPI);
-#endif /* CONFIG_SERIES_STM32F7X */
+#endif /* USB_HS_PHYC */

#endif /* CONFIG_USB_HS_BASE_ADDRESS */
USB_HS_PHYC is not defined on all STM32F7 SoCs, so enabling ULPI clock
if it is defined won't
work on other SoCs.
The idea is to disable the ULPI clock for SoCs which do not have an HS
PHY, as the FS PHY should be used instead. If USB_HS_PHYC is defined,
the SoC has an HS PHY but not FS PHY, when it is not defined, it has a
FS PHY but no HS PHY.

@@ -285,7 +282,11 @@ static int usb_dc_stm32_init(void)
#endif
usb_dc_stm32_state.pcd.Init.dev_endpoints = CONFIG_USB_NUM_BIDIR_ENDPOINTS;
usb_dc_stm32_state.pcd.Init.speed = USB_OTG_SPEED_FULL;
+#ifdef USB_HS_PHYC
+ usb_dc_stm32_state.pcd.Init.phy_itface = USB_OTG_HS_EMBEDDED_PHY;
+#else
usb_dc_stm32_state.pcd.Init.phy_itface = PCD_PHY_EMBEDDED;
+#endif /* USB_HS_PHYC */
usb_dc_stm32_state.pcd.Init.ep0_mps = USB_OTG_MAX_EP0_SIZE;
usb_dc_stm32_state.pcd.Init.vbus_sensing_enable = DISABLE;
The PR is focused on enabling FS mode on OTG_HS that's why I didn't
change PHY interface.
I understand that, that's why my patch didn't change USB_OTG_SPEED_FULL
(but I have verified it work in HS mode). That said given that there is
no FS PHY when there is an HS PHY, we need to use it in FS mode instead.

Aurelien

--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurelien@aurel32.net http://www.aurel32.net

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