Re: MIPS architecture support
Its been a long time.
On Oct 11, 2018, at 8:04 PM, Kumar Gala <kumar.gala@...> wrote:The company that I currently work for makes SoCs. However, they are not ready toOn Oct 11, 2018, at 8:14 PM, Alex Nemirovsky <alex.nemirovsky@...> wrote:Is this for a customer SoC or some generally available MIPS SoC?
release the SoC specific code upstream.
For now, they would like to support a generic QEMU-MIPS board based on standard MIPS R3k architecture (ISA I, II) with generic QEMU drivers (i.e. serial port)
I’m been maintaining MIPS support here since Zephyr 1.7. I’ll look over the code to see if there is anything we should reuse.However, before I begin the process, I’ll like to know if anyone else is working on this as well so that we could coordinate our efforts.There was some MIPS support contributed but never finished off. Here’s a link to the GitHub PR:
btw, Most of our support is similar to the Zephyr RISCV implementation from an architecture point of view. i.e. swap() function using syscall exception.
Also, would you be able to act as a maintainer for the port?I have a private Zephyr SDK 0.9.3 built for our MIPS SoC with some custom instructions. However, for upstream
management would just like to support stock MIPS ISA I, II, etc without adding our custom instructions to the toolchain.
Other stock ISA like MIPS32, MIPS64 is fine also.
I could act as a maintainer for the MIPS architecture, if you like.
What do you think about the generic MIPS support using QEMU for now instead of physical HW?