Re: 回复:[Zephyr-devel] Is The tick handler "z_clock_announce" in SMP mode dupulicate caculated?


Andy Ross
 

Indeed, that looks like a bug in the driver when SMP and !TICKLESS are set.  Can you file an issue on github?


Andy


On 8/24/2019 3:23 AM, "曹子龙 wrote:
Hi andrew:
 
   i find the place you said laste emai, it seems only xtensa and x84 arch supports the SMP mode, so take xtensa for exmaple.

it seems the mechanism you said in the laste email only effect when "CONFIG_TICKLESS_KERNEL" enabled.
if the macro CONFIG_TICKLESS_KERNEL not enabled,  the z_clock_announce still pased the 1 tick for each core, so the cur_tick would be doubled, where am i wrong?

 thanks for your kindly help.

static void ccompare_isr(void *arg)
{
    ARG_UNUSED(arg);

    k_spinlock_key_t key = k_spin_lock(&lock);
    u32_t curr = ccount();
    u32_t dticks = (curr - last_count) / CYC_PER_TICK;

    last_count += dticks * CYC_PER_TICK;

    if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL) ||
        IS_ENABLED(CONFIG_QEMU_TICKLESS_WORKAROUND)) {
        u32_t next = last_count + CYC_PER_TICK;

        if ((s32_t)(next - curr) < MIN_DELAY) {
            next += CYC_PER_TICK;
        }
        set_ccompare(next);
    }

    k_spin_unlock(&lock, key);
    z_clock_announce(IS_ENABLED(CONFIG_TICKLESS_KERNEL) ? dticks : 1);
}


曹子龙

珠海全志科技股份有限公司      BU1-PSW

地址:广东省珠海市高新区唐家湾镇科技2路9号

TEL:13824125580

Email:caozilong@...

网址: http://www.allwinnertech.com

 


------------------------------------------------------------------
发件人:Andy Ross <andrew.j.ross@...>
发送时间:2019年8月23日(星期五) 23:35
收件人:曹子龙 <caozilong@...>; devel <devel@...>
主 题:Re: [Zephyr-devel] Is The tick handler "z_clock_announce" in SMP mode dupulicate caculated?

This is the responsibility of the timer driver.  The ticks announced needs to be globally correct.  The existing drivers do this by locking a "last count" state variable and updating it, so they see the updates made by the other cores.


Andy


On 8/23/2019 8:14 AM, "曹子龙 wrote:
Hi  friends:
    
  a puzzle in the timer tick interrupt handler in SMP mode.  look at below,  the SMP mult cores share the same "cur_tick" object to remeber the current time, each cpu would increment it when the tick hander  excutes on each CPU.
so, could this would accelerate the timer compare with the realworld?  for example, if 4cores  exist, the cur_tick would 4 times incmrent than the read world, i cant fingure out where am a wrong, so, could you figure me out?  thanks for your kinldy supply. 

void z_clock_announce(s32_t ticks)
{
#ifdef CONFIG_TIMESLICING
 z_time_slice(ticks);
#endif

 k_spinlock_key_t key = k_spin_lock(&timeout_lock);

 announce_remaining = ticks;

 while (first() != NULL && first()->dticks <= announce_remaining) {
  struct _timeout *t = first();
  int dt = t->dticks;

  curr_tick += dt;
  announce_remaining -= dt;
  t->dticks = 0;
  remove_timeout(t);

  k_spin_unlock(&timeout_lock, key);
  t->fn(t);
  key = k_spin_lock(&timeout_lock);
 }

 if (first() != NULL) {
  first()->dticks -= announce_remaining;
 }

 curr_tick += announce_remaining;
 announce_remaining = 0;

 z_clock_set_timeout(next_timeout(), false);

 k_spin_unlock(&timeout_lock, key);
}




曹子龙

珠海全志科技股份有限公司      BU1-PSW

地址:广东省珠海市高新区唐家湾镇科技2路9号

TEL:13824125580

Email:caozilong@...

网址: http://www.allwinnertech.com

 



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