Re: ARM Cortex R intermittent MPU memory access check failures with CONFIG_USERSPACE
+ Andrew, Stephanos
Thanks for reporting this. I need to do a more careful looking into it, but it is likely that you have spotted a bug in the Cortex-M implementation.
The implementation of mpu_buffer_validate() has not changed since its initial porting – it seems that it does not protect writing RNR and then accessing RBAR, RASR registers aferwards and that seems to have always been the case.
So a thread context-switch interrupting this operation may modify the RNR register, making the read of RBAR, RASR or RLAR (v8m) inside the functions called by mpu_buffer_validate() invalid.
If mpu_buffer_validate() is called by thread supervisor mode, it needs to be protected by locking IRQs. In fact, only the PendSV needs to be lock because only that one does MPU reprogramming.
Alternatively RNR could be saved and restored in PendSV handler (normal IRQs do not touch MPU).
I’d appreciate if you file a bug report for this for Cortex-M.
For Cortex-R, user mode is not assumed to be working (yet) so, strictkly speaking, it is not a bug, but if you work on Cortex-R user mode, this is one thing you need to consider!
From: devel@... [mailto:devel@...] On Behalf Of phil.erwin via Lists.Zephyrproject.Org
Sent: Monday, January 27, 2020 9:38 PM
Subject: [Zephyr-devel] ARM Cortex R intermittent MPU memory access check failures with CONFIG_USERSPACE
I'm getting intermittent run-time failures such as: