Just a quick note that being the ARMv7/Cortex-A still a 32bit arch, that is probably closer to the current ARMv7/Cortex-R work than to my ARMv8/Cortex-A work.
To my knowledge, the most significant differences are MMU vs. MPU and the newer interrupt controller in the Cortex-R, which expanded the old controller's basic secure/non-secure model into a multiple-priority model. Other than the FPU stuff, I didn't mess much with the assembly code that implements the context switch.
Did you try to use the Zephyr SDK?
My memory on that is a bit hazy, as I started back in November, but to my best recollection I followed the standard 'getting started' procedure at first, including the SDK setup. Yet, the first Zephyr-compatible board I came across at work was an NXP eval kit based around a Cortex-M33 (the LPCXPRESSO55S69), and compiling the demos with the supplied cross-compiler failed as it did not yet support the M33. That's how I ended up with the alternative ARM toolchain as described in the "3rd party toolchains" section. I can easily set up a fresh development VM and give the Zephyr SDK another try, as the A9 is a proven piece of hardware that has long been supported.
What's the issue with the remaining tests?
Fortunately, there's no technical issue here - it's just an issue of me not yet having had time to read up on how the test framework works.
Are you able to use QEMU to emulate a working hardware?
The QEMU template for the Zynq7000 supports all important components (GIC, TTC, UART) plus the two Ethernet controllers. There's also USB which I'm not looking at right now, plus some SPI/I2C support mostly relevant for flash memory connectivity. While the bitstream programming of the FPGA can be simulated, IP cores such as the GPIO don't seem to be on board, so GPIO won't work while the rest will.
IMO the next step is making sure you are able to pass as many tests as possible in a QEMU environment when using the Zephyr SDK.Will do, but prior to that I'll most likely start by updating my codebase and merging my changes into the new AARCH32/AARCH64 structure. I guess with separate assembly code for each architecture's context switch, that part might be a lot more uncluttered compared to what I have right now.
Thanks for the advice!