Arch: RISC-V PMP on Qemu


antmc@...
 

Hello,
 
I am new here and I don't know if this is the right place to ask these kind of questions, if not, sorry!
 
Me and my friend are currently doing our thesis about RISC-V and the latest standard with physical memory protection (PMP) on embedded systems with no MMU. For this, we are using Zephyr RTOS (we have cloned the git repo) and the qemu_riscv32. We have currently not done any bigger changes to the kernel and arch files for RISC-V, instead we have created a small API that will set up the PMP registers, go to U-mode, test it etc. Now, to my main question: Does the qemu_riscv32 support the latest RISC-V standard? I wonder because when debugging, the pmp registers are all set and seems to be correct but sometimes the permissions are completely ignored. Maybe we have understood the RISC-V specification wrong... 
 
Example case:
A thread is created and the pmp registers are set to e.g. only allow RW to the stack region and RX to the code region (we use A-TOR to set the ranges). For the code region it seems to work as expected in most cases (Remove the X permissions raises a fault etc). But for the stack region it does not work when trying to execute a binary located in the stack (i.e. the binary gets executed even though there is no X permissions).
 
Thanks!

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