Re: [RFC] SMP support for RISC-V privilege architecture

Katsuhiro Suzuki

Hello Kumar,

Sorry for multi posting. Zephyr ML has very long delay to deliver my mail...??

Anyway, thanks a lot for your comment.

On 2020/10/06 23:57, Kumar Gala wrote:

On Oct 6, 2020, at 4:04 AM, Katsuhiro Suzuki <> wrote:

Hello All,

I'm working on SMP support for RISC-V privilege architecture.

It seems worked well on QEMU RV32 virt pc (*) porting.
(RV64 not tested yet)

But I don't understand Zephyr's SMP mechanism perfectly and
don't know required conditions (Ex. regression tests) if I
want to change these area.

I'm welcome comments or review of my patch.

(*)QEMU RV32 virt pc:

Diffs of config from default:

Command line:
qemu-system-riscv32 -nographic -machine virt -net none \
-chardev stdio,id=con,mux=on -serial chardev:con \
-mon chardev=con,mode=readline -kernel zephyr/zephyr.elf \
-cpu rv32 -smp cpus=4 -bios none

Best Regards,
Katsuhiro Suzuki
Would probably be good to add a second SMP config for qemu_riscv32 for SMP=y. You can look at the boards/x86/qemu_x86 to see examples of having different configs.
I'll add the config.

BTW, QEMU can choose SMP mode or non-SMP mode by command option.
qemu_x86 Zephyr users never want to use non-SMP mode?

I remember a help of CONFIG_USE_SWTCH said that:
"In uniprocess situations where the
architecture provides both, _arch_switch incurs more somewhat
overhead and may be slower.".

I think RISC-V may cover high-end from low-end, so I try to keep
old style context switch mechanism. On the other hand, it seems
x86_64 port don't implement old style.
Should we keep old one or it depends on each architectures?

As for testing, I’m guessing the main test to make sure runs and passes is tests/kernel/smp.
Andrew, can probably mention other tests or aspects to be aware of.
Thanks! I'll try it and report results.

- k
Best Regards,
Katsuhiro Suzuki

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