Re: [RFC] SMP support for RISC-V privilege architecture
Sorry for multi posting. Zephyr ML has very long delay to deliver my mail...??
Anyway, thanks a lot for your comment.
On 2020/10/06 23:57, Kumar Gala wrote:
I'll add the config.On Oct 6, 2020, at 4:04 AM, Katsuhiro Suzuki <email@example.com> wrote:Would probably be good to add a second SMP config for qemu_riscv32 for SMP=y. You can look at the boards/x86/qemu_x86 to see examples of having different configs.
BTW, QEMU can choose SMP mode or non-SMP mode by command option.
qemu_x86 Zephyr users never want to use non-SMP mode?
I remember a help of CONFIG_USE_SWTCH said that:
"In uniprocess situations where the
architecture provides both, _arch_switch incurs more somewhat
overhead and may be slower.".
I think RISC-V may cover high-end from low-end, so I try to keep
old style context switch mechanism. On the other hand, it seems
x86_64 port don't implement old style.
Should we keep old one or it depends on each architectures?
As for testing, I’m guessing the main test to make sure runs and passes is tests/kernel/smp.Thanks! I'll try it and report results.
- kBest Regards,