Re: RISC-V maintainers and collaborators


Katsuhiro Suzuki
 

Hello Maureen-san,

I have one question.

Who is most suitable person if we want to discuss or merge RISC-V subsystem and
RISC-V related drivers (not core kernel)?

It seems that mainly Nashif and Gala do merging non-trivial PRs.
I understand they are very busy to review and maintain high priority regions such
as x86, ARM and other major drivers (network, USB, etc.).

So if there are other persons who can merge PRs I want to know and working with them...

Best Regards,
Katsuhiro Suzuki

On 2020/11/10 5:52, Maureen Helm wrote:
Hi everyone,
We are looking for collaborators and maintainers to help maintain the RISC-V architecture in Zephyr, and have several major RISC-V pull requests (SMP and memory protection) in acute need of code review. If you are interested in taking on one of these important roles and helping to advance RISC-V support in Zephyr, I encourage you to review the TSC Project Roles [1], start reviewing RISC-V pull requests [2], and consider adding yourself as a collaborator in MAINTAINERS.yml. Active collaborators are encouraged to become maintainers with TSC approval.
[1] https://docs.zephyrproject.org/latest/contribute/project_roles.html
[2] https://github.com/zephyrproject-rtos/zephyr/pulls?q=is%3Apr+is%3Aopen+label%3A%22area%3A+RISCv32%2F64%22
Maureen

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