Re: [EXT] Re: [Zephyr-devel] Exclusive instruction LDAXR for ARM64 used by Zephyr SMP

Jiafei Pan

Thanks, the following patch fixed this issue, it is similar with my original
patch to avoid to use spin lock before enable MMU,

aarch64: mmu: don't touch the lock before the MMU is on

We can't do atomic memory operations before the MMU is on. Let's create
a code path to set up MMU page tables without any lock. There is
obviously no concurrency issues at this stage.

Signed-off-by: Nicolas Pitre <>

Best Regards,

-----Original Message-----
From: Nicolas Pitre <>
Sent: Saturday, April 10, 2021 8:56 AM
To: Jiafei Pan <>
Subject: [EXT] Re: [Zephyr-devel] Exclusive instruction LDAXR for ARM64 used
by Zephyr SMP

Caution: EXT Email

Please re-test with the latest upstream. Incidentally, a fix was merged today
to solve this problem.

On Fri, 9 Apr 2021, Jiafei Pan wrote:

Hi, All,

I am debugging Zephyr SMP on ARM64, but currently I found arm64 LDAXR
instruction is used in spin lock function, but I found there is different behavior
on different platform.

Here is calling line:

__start --> z_arm64_prep_c --> z_arm64_mmu_init --> setup_page_tables
--> add_arm_mmu_flat_range --> add_map --> set_mapping --> key =

The issue is on one ARM A72 platform, there will be "Unknown Exception"
(ECR.EC = 000000) with this calling flow, I found the exception is caused by
LDAXR instruction, and MMU is disabled when exception occurs. When I
enabled MMU firstly and then call LDAXR instruction, there will be no such

But on another A53 platform, there is no such issue both for the case MMU
is disabled or enabled.

So I am not sure whether there is some relation with MMU and LDAXR
instruction, and I don't find more information in ARM's document, I have
worked out one patch to avoid to use LDAXR and STLXR before enable MMU,
but I want to find out whether it is the root cause of the issue.

Any comments or suggestion is welcome, thanks.

Best Regards,

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