Re: Support for Ambiq Apollo chips #bluetooth #ambiq

Keith Short

The GPIO driver for the ITE IT8xxx2 family also interleaves the register space.

You could follow the model used for that driver - create multiple reg phandles for the individual registers.


On Sun, Apr 25, 2021 at 4:19 PM <ciesielskimm@...> wrote:

I'm trying to add support for the Ambiq Apollo series chips. I'm new to the Zephyr and not very experienced with Device Tree format.
Currently I'm working on the zephyr/dts/arm/ambiq/apollo.dtsi. I'm trying to add the GPIO control registers. I'm modyfing
the STM32 dtsi file. STM32's define the GPIO control in a different way. All the Pad A registers are defined in a continous memory block.
In Ambiq SOCs those they are interleaved. The image below shows the memory map.

First its the Pad configuration registers. Then its GPIO configuration register. I'm wondering how should I implement this
memory layout in the dtsi.

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