From: Andreas Kölbl <andreas.koelbl@...regensburg.de>

This change fixes the prescaler values in the defconfig. The prescaler values
shown in the technical reference manual (STM32F407xx, p.19) differ from those in
the defconfig which results in wrong timer delays.

Signed-off-by: Andreas Kölbl <andreas.koelbl@...regensburg.de>
---
For further information about the fix look at
https://lists.zephyrproject.org/pipermail/zephyr-users/2017-July/000618.html

 boards/arm/stm32f4_disco/stm32f4_disco_defconfig | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/boards/arm/stm32f4_disco/stm32f4_disco_defconfig b/boards/arm/stm32f4_disco/stm32f4_disco_defconfig
index f67fa14ed..6290c8e19 100644
--- a/boards/arm/stm32f4_disco/stm32f4_disco_defconfig
+++ b/boards/arm/stm32f4_disco/stm32f4_disco_defconfig
@@ -27,10 +27,10 @@ CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
 # use HSE as PLL input
 CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
 # produce 168MHz clock at PLL output
-CONFIG_CLOCK_STM32_PLL_M_DIVISOR=4
-CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=72
+CONFIG_CLOCK_STM32_PLL_M_DIVISOR=8
+CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=336
 CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2
-CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=3
+CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=7
 CONFIG_CLOCK_STM32_AHB_PRESCALER=1
-CONFIG_CLOCK_STM32_APB1_PRESCALER=2
-CONFIG_CLOCK_STM32_APB2_PRESCALER=1
+CONFIG_CLOCK_STM32_APB1_PRESCALER=4
+CONFIG_CLOCK_STM32_APB2_PRESCALER=2
--
2.13.3

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