On 8 August 2017 at 10:52, massimiliano cialdi
<massimiliano.cialdi@powersoft.it> wrote:

this make sense (but the address of RCC_APB1RSTR is 0x20)

But this raises the question: where is it defined STM32_CLOCK_BUS_APB1 and
how?

Grepping the entire zephyr source I find:

#define STM32_CLOCK_BUS_APB1 2

in file zephyr/include/dt-bindings/clock/stm32_clock.h

that is not 0x20 as I expect

Looking at the drivers/clock_control/stm32_ll_clock.c, they use switch
statements to steer the programming for the clock enables. The actual
call makes a macro/function call to set the enable bit. So in this
case, the device tree denotes the switch value to use and the bit
mask.

I was assuming they were using the offsets. that isn't the case.
they are using ext hal code selected via the switch.

Sorry bout that.

Andy