RISC-V: mtvec: Vectored Mode

William <wpatty24@...>

Hi all,

I would like to add support for "vectored mode" of the Machine Trap-Vector Base-Address Register (mtvec) to the RISC-V architecture — at the SOC level. Some SOCs have already implemented this directly. It makes sense to centralize this feature since it could be reused for all RISC-V SOCs. Additionally, centralizing the feature would allow RISC-V to support Zephyr’s ‘direct’ IRQ feature when vectored mode is used. Im interested to hear if others agree that this feature would be useful.

For background purposes, I’m working on a project that uses the lowRISC Ibex processor. This processor implements the RISC-V Privileged Architecture specification; however, it doesn’t support mtvec direct mode, only vectored mode.

Given that the vectored mode is in the RISC-V Privileged Architecture specification, it should be supported within the RISCV_PRIVILEGE SOC family. 

Here’s what I’m proposing:

  • Add ‘config RISCV_MTVEC_VECTORED_MODE to “soc/riscv/riscv-privilege/Kconfig’; default will be DIRECT_MODE which is how it is implemented currently
  • Add preprocessor conditions to handle both cases within “soc/riscv/riscv-privilege/common/vector.S”
  • Take advantage of CONFIG_GEN_IRQ_VECTOR_TABLE to generate the vector table to use for mtvec
  • For vectored mode, mtvec will be set to the address of the Zephyr generated IRQ Table (_irq_vector_table symbol)
  • Add a default implementation for _isr_wrapper that’s simply a jump to __irq_wrapper; RISC-V uses CONFIG_GEN_SW_ISR_TABLE.
  • [Future] Enable Zephyr’s ‘direct’ IRQ feature when VECTORED_MODE configuration is set. There are more specifics to discuss here but that can wait until if / when this feature is added. 

However, there is one aspect that’s more complicated:

  • Per the RISC-V Privileged Architecture specification, setting vectored mode may impose additional alignment constraints on the address stored in mtvec. This implies that each processor can have it’s own alignment constraints. If we want to take advantage of Zephyr’s CONFIG_GEN_IRQ_VECTOR_TABLE option, we would need to force correct alignment on _irq_vector_table symbol. We should decide on a “good default” but have a mechanism where alignment could be changed for a specific SOC series. It probably makes sense to enforce the alignment in the default RISC-V linker script. However, linker scripts are not my strong suit and I’m not confident on the approach for this aspect of the change. Any ideas would be welcomed.

I appreciate you taking the time to read this. I look forward to any discussion this proposal might create.


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