Date   

Re: [RFC] Provide a generic interface for getting the SOC ID and version

Kumar Gala
 

On Aug 17, 2016, at 5:20 AM, Nashif, Anas <anas.nashif(a)intel.com> wrote:

Did not expect this to generate such a big discussion. Here is a use case in addition to what was mentioned in the thread below. Think of this API as a helper API for higher lever features and not a way to select/deselect features based on HW.
I’d rather see the higher level feature that needs this first. Meaning, show me patch series that needs this info and than it will become far more clear what we should be doing. Until than I don’t think just adding a new API makes sense.

Depending on the HW/MCU being used, getting the hardware information such as model number, vendor ID, hardware revision might vary in complexity so implementing this for supported SOCs makes a lot of sense using an API that can be used by applications and higher level features such as IOT protocols. Originally this ZEP was created to prepare for LWM2M and specifically the device profile:

http://dev_devtoolkit.openmobilealliance.org/IoT/LWM2M10/doc/TS/index.html#!Documents/lwm2mobjectdevice.htm

To prepare for the implementation of the profile and to avoid implementing this for the various MCUs in different places where it can be used, the API was proposed.
For LWM2M is using SoC info actually the right choice? Should this be board specified?

Feeding this type of data at build time is always an option, but I do not think it makes sense in this case and especially when the HW has lots of information stored already that would make it very difficult to fill in at build time. Doing this at build time will encourage developers and users to enter random data and things like TODO or XYZ all over the place, just to get their app to build and move on. Why bother if the data is already provided by the hardware?

Uniqueness of the data is not key here, multiple boards of the same HW might end up generating the same ID, however, this depends on the hardware and some cases such data can be combined with other sources to achieve this.
I’m not sure I follow why uniqueness isn’t key.



Anas






On 29/07/2016, 23:48, "Kumar Gala" <kumar.gala(a)linaro.org> wrote:

If what you are talking about is really for errata than I think we should solve that specific problem. I think a combination of a consistent #define naming and usage convention:

#define CONFIG_ERRATUM_<VENDOR_NAME>_<CHIP>_<VND/CHIP SPECIFIC ERRATUM DESC>

For cases that could be handled at compile time. Than for runtime cases:

Something like:

bool has_erratum(enum erratum_list e).

where erratum_list can be defined in some SoC specific header and code to report if the given erratum is valid on the given chip.

Also, for what you describe, only the revision info is need so at most we’d have an internal API like:
uint32_t __get_soc_revision(void)

- k

On Jul 28, 2016, at 11:01 AM, Vij, Gajinder S <gajinder.s.vij(a)intel.com> wrote:

I'm confused as to what you mean by using features. Do you mean major silicon features such as different Cache size or different HW acceleration blocks? These would likely be a major rev of the silicon which would warrant a new binary. Also, how are silicon features determined without reading the underlying SOC version?

The origin of the request for the API is for a very specific scenario. When SOC vendors bring up new silicon, there are often multiple revisions of silicon available to the dev/test team before the chip is commercially available. Early versions of the silicon invariably have hardware bugs and the driver SW needs to compensate. As new iterations of the silicon are available to the dev/test team, either run-time detection is used to apply/disable the HW work-arounds, or the older HW boards become deadweight. This has significant cost and efficiency implications. This API is intended to be used at a very low level to allow drivers to enable/disable HW work-arounds. Having the API in the kernel saves the dev team from deriving their own API. I've seen scenarios where different component teams on the same project each implement their own SOC version detection scheme for this purpose.

The API is not intended for use by applications, and is not intended to distinguish between major chipset releases (example, not intended to distinguish between 384 vs a 486, or a Cortex M0 vs a Cortex M4). I'm still confused as to why a developer go through the trouble to have a single binary that runs on significantly different systems. This would be an inefficient use of FLASH and Memory, unnecessarily increasing cost of the end device.

I maintain that if an OEM picks up new silicon that has additional functionality, there will be a new HW board to enable new features/sensors, a new display etc. The OEM will naturally go through the process to create a separate binary. They may decide to use the same code-base to create multiple binaries, but that will be at compile-time, and won't require run-time detection to distinguish code-paths. It is _more_ work to create a single binary that runs on multiple HW SKUs, and a _lot more_ work to create a single binary that runs on two platforms that are significantly different.

Can you provide an example of an API that would provide feature level granularity?

Thanks,
Gajinder



-----Original Message-----
From: Kumar Gala [mailto:kumar.gala(a)linaro.org]
Sent: Thursday, July 28, 2016 6:25 AM
To: Vij, Gajinder S <gajinder.s.vij(a)intel.com>
Cc: Morgaine <morgaine.dinova(a)googlemail.com>; devel(a)lists.zephyrproject.org
Subject: Re: [devel] [RFC] Provide a generic interface for getting the SOC ID and version

The use case you specify of picking SOC-version-specific code at run-time should be using features and not an ID for determining such things. This goes directly to Tixy’s email thread which I agree with 100%.

- k

On Jul 22, 2016, at 8:02 PM, Vij, Gajinder S <gajinder.s.vij(a)intel.com> wrote:

There is a clear use case for the API, as articulated by Morgaine and Pedro (included below). The purpose of the API is to provide the mechanism for a developer to be able to select SOC-version-specific code paths at run-time, reducing the need for a custom image per SOC version. When and if version specific code is used depends on the circumstances and should be left to the developer as a policy decision.

I’d like to determine if there is still objections to this API being implemented in Zephyr. I read through the thread and will attempt to address the concerns raised.

On the concerns articulated by Tixy, since the App, Kernel, and BSP are all compiled from source into a single binary, I don’t see the same app compatibility issues cropping up in a Zephyr scenario that have come up in Linux. It is conceivable that someone may attempt to use the SOC version as a way to distinguish between different variants of a product family, but that would be an inappropriate use of the API.

I don’t know where the notion of using this API as an entropy source came from. I have removed this from the Jira description.

To the question about forward support and uniqueness of the IDs – should this happen on different architectures, I don’t see a problem because I expect the BSPs will still be unique, and therefore I don’t expect a binary run on one platform to successfully be run on another.

Comments welcome.

Thanks,
Gajinder


Pedro’s use case:
Ø The user might know the SOC ID at compile time (although a user might want to check against the hardware in case of doubt).
Ø The SOC revision can change between hardware stepping, so the user might not know at compile time the version of a given model.
Ø In that case reading the hardware registers is the only way to know the revision.

Morgaine’s use case:
Ø This API creates a 1:N relationship between compiled firmware and target behaviour. In other words it allows target behaviour to be parametrized by some target identifier in a standard way given by the API, without requiring each different target to be loaded with different firmware.



From: Morgaine [mailto:morgaine.dinova(a)googlemail.com]
Sent: Thursday, July 21, 2016 10:27 AM
To: devel(a)lists.zephyrproject.org
Subject: [devel] Re: [RFC] Provide a generic interface for getting the SOC ID and version

Kumar writes:
So I ask again, what are we trying to accomplish?
See my preceding reply, which explored exactly that question.

From the original requirement expressed in the RFC and from Tixy's subsequent comments, it's clear that there are at least two distinct purposes in people's minds: the one mentioned in the RFC which required uniqueness for generating unique per-target data, and another purpose related to feature sets. It was noted that the second of these is somewhat problematic.

My interest is in the simpler of these, the requirement expressed in the RFC, because it is such a common need. Someone else will have to argue in favour of the other if they feel it's important. The two could of course be combined if the agreed data width permits.

Morgaine.


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MERGED within last 24 hours:


[RFC] Hardware crypto APIs

Joseph, Jithu
 

The purpose of these APIs, is to provide applications, a hardware independent way to perform encryption/decryption (ZEP-328 - https://jira.zephyrproject.org/browse/ZEP-328 ).
In other words Crypto hardware drivers implement functions as mandated by the header file, and apps can use the standard driver model way to open the crypto device and invoke functions (defined in the header), to realize cipher operations (encryption/decryption), using standard cipher modes like ECB, CBC, CTR etc.

Here are the list of patches and what they do :

1. cipher.h header (https://gerrit.zephyrproject.org/r/#/c/3311/ ) - defines the cipher interface for encryption/decryption.

2. Sample driver - https://gerrit.zephyrproject.org/r/#/c/3312 -A sample driver using the above interface (and using tinycrypt s/w library for actual encryption)

3. Sample app - https://gerrit.zephyrproject.org/r/#/c/3313/ - Sample app using the crypto interface

Cipher.h primer - Apps are meant to first open a context, by specifying one time parameters like key, algorithm and modes (via cipher_ctx struct). These one-time parameters are used to program the hardware crypto block . The driver returns the corresponding encryption, decryption functions pointers relevant to the chosen mode. Subsequently, apps can invoke them (multiple times) using standard "mode" functions defined in the header. The below sequence diagram tries to portray this pictorially. (You will need to enable fixed font size in mail client to see it as intended . e.g on outlook File > Options > Mail > Stationery and Fonts > Set the font for plain text e-mails to a monospaced font (say) Courier New. )

+-------------------------------------------------------------------------------------------------+
| +-------+ +---------+ +-------------+ |
| | App | |Crypto | | Crypto | |
| +---+---+ |Driver | | H/W block | |
| | +----+----+ +-------+-----+ |
| | | | |
| +-------------------------------------------------------------------------------------+ |
| | | Session Context setup phase | | | |
| +-------------------------------------------------------------------------------------+ |
| | +--------------------------------+ | | |
| | |cipher_begin_session(*dev, *ctx)| | | |
| +---------->where: +------> program h/w | |
| | |ctx -> Key, Algo type, mode etc | +----+with one time->| |
| | +--------------------------------+ | parameters | |
| | | | |
| | returns function pointers corresponding | | |
| <-------to the selected mode in ctx->ops <-----+ | |
| | | | |
| +-------------------------------------------------------------------------------------+ |
| | |Operation Phase (possibly repeated multiple times)| | | |
| +-------------------------------------------------------------------------------------+ |
| | +------------------------------+ | | |
| | | cipher_xx_yy(*ctx, *pkt, ..) | | | |
| +---> | where: | | | |
| | +---------> Pkt -> Input/Output buffers +---------> | |
| | | | xx -> mode (ecb,cbc, ctr etc)| +--------------------> |
| |nex| | yy -> encrypt / decrypt | <--------------------+ |
| |op | | .. -> IVs, CTRs (mode spec) | | | |
| | | +------------------------------+ | | |
| ^ | | | |
| | Provide the result | | |
| | | <------------------------------------------------+ | |
| +---+ | | |
| +------------------------------------------------------------------------------------+ |
| | | Session Freeing phase | | | |
| +------------------------------------------------------------------------------------+ |
| | | | |
| | cipher_free_session(*dev, *ctx) | | |
| +------------------------------------------------> | Clear session info |
| | +---from h/w---------> |
| | | | |
| <--------------------------------------------------+ | |
| | | | |
| | | | |
| -------------------------------------------------------------------------------------------+ |
| +---v---+ +---------+ +-------v-----+ |
| | App | |Crypto | | Crypto | |
| +-------+ |Driver | | H/W block | |
| +---------+ +-------------+ |
| |
| |
+-------------------------------------------------------------------------------------------------+

This interface is expected to evolve as SOCs with hardware crypto support start coming in (with possibly newer requirements) , the current API is intended as a starting point. Comments are welcome.


Thanks
Jithu


[Acknowledgments : Geoffrey Thorpe <geoff.thorpe(a)nxp.com> and Tomasz Bursztyka <tomasz.bursztyka(a)linux.intel.com>, for their initial review comments on gerrit ]


Re: Proposal to streamline GPIO, Pinmux driver API

Liu, Baohong
 

Hi,

-----Original Message-----
From: Piotr Mienkowski [mailto:Piotr.Mienkowski(a)schmid-telecom.ch]
Sent: Friday, September 2, 2016 3:22 AM
To: devel(a)lists.zephyrproject.org
Subject: [devel] Proposal to streamline GPIO, Pinmux driver API

Hello Community,

I would like to discuss GPIO / Pinmux driver combo which I believe become
overcomplicated and may be confusing for a regular user.

The current API seems to be designed around Intel Quark architecture and
QMSI SDK. In Quark there are separate Pinmux and GPIO modules and so we
got separate Pinmux and GPIO drivers. However, in most chipsets GPIO
module takes care of both PIO (reading/writing from/to a pin) and pin
muxing (connecting pin to a peripheral/PIO controller). By now the functional
split between the two drivers become blurred and is overlapping.

Some examples:

At present GPIO driver defines GPIO_PUD_PULL_UP (Enable GPIO pin pull-
up) to be used with gpio_pin_configure() function and Pinmux driver has
pinmux_pin_pullup() function. Both are meant to do the same thing
however gpio_pin_configure() will not work with Intel Quark chips and
pinmux_pin_pullup() will mostly not work with other chips e.g.
Freescale/NXP FRDM-K64F. Still some chipsets e.g. Atmel SAM3x implement
both functions but then even for Atmel SAM3x setting pin pull-down is only
possible via gpio_pin_configure() function.

pinmux_pin_input_enable() function is used by Quark chips to
disable/enable input pad and gpio_pin_configure() to set pin as input or
output. This is not easily rendered from the function's name/description and
in fact Atmel SAM3x driver implements pinmux_pin_input_enable() to
configure pin as input or output overlapping it with the same functionality
provided by gpio_pin_configure().

In case of ARM based chips e.g. Atmel SAM3x, Freescale/NXP FRDM-K64F to
configure pin with pull-up and connect it to external peripheral one needs to
call pinmux_pin_set() which takes as an argument pin index, e.g. pin PB2,
third pin on port B would have index 34 and gpio_pin_configure() which
takes as an argument port and port's pin number, e.g. PB2 has number 2. So
in two subsequent calls we need to use different pin values even if we
operate on the same pin. While this may be convenient for Quark chips it is
not for other chip families.

Currently it is not really possible to know which function should be used
when and how without analyzing Zephyr's source code.

I believe that split between Pinmux and GPIO driver is not a good general
solution and in case we preserve the current API it will soon become even
more convoluted.

I would like to propose to phase out Pinmux driver and implement pin
multiplexing in GPIO driver. That would require adding something like
GPIO_FUNC_A, ..., GPIO_FUNC_D to GPIO API.

Other possibility would be to limit Pinmux driver only to architectures that
really need it, like Quark chips. Having pin multiplexing available
simultaneously in GPIO and Pinmux driver will be confusing for Quark users,
however that's already the case with pull-up configuration.

I haven't created a Jira issue, neither RFC in Gerrit yet. At first I would like to
get a quick feedback if you find my arguments sensible.

Thanks,
Piotr
Some confusion does exist when these APIs are used across platforms.
But, for QUARK, the boundary is clear and there is no overlapping;
Combining them into one is not conceptually right.


Re: How to handle a board with a dozen SoC's?

Jon Medhurst (Tixy) <tixy@...>
 

On Fri, 2016-09-02 at 15:29 +0000, Nashif, Anas wrote:
Ok, there is a JIRA about board/soc structure documentation already
and it happens to be assigned to me, I will address this ASAP
Thanks, that would be helpful. I've been using existing code as examples
and decoding Makefiles to see what's possible, but I'm aware that the
end result would probably not be a desirable or 'best' solution :-)

My situation is also the inverse of the normal common SoC being used on
multiple boards, as I have multiple SoC's custom made for a fixed board.

--
Tixy


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https://jira.zephyrproject.org/browse/ZEP-546

[ZEP-471] (Fixed) Ethernet packet with multicast address is not working
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[ZEP-730] (Fixed) Zephyr documentation page references 1.5.0, but it's not yet released
https://jira.zephyrproject.org/browse/ZEP-730


Re: How to handle a board with a dozen SoC's?

Nashif, Anas
 

Ok, there is a JIRA about board/soc structure documentation already and it happens to be assigned to me, I will address this ASAP, this might help you with the issue below.

Anas

On 2 Sep 2016, at 11:23, Jon Medhurst (Tixy) <tixy(a)linaro.org> wrote:

On Fri, 2016-09-02 at 15:46 +0100, Jon Medhurst (Tixy) wrote:
I'm trying to add Zephyr support for a board [1] where the 'SoC' is an
FPGA that can be programmed with a dozen different CPU types and varying
support IP, and I'm wondering how to organise this.
I realised this and $subject may be a bit ambiguous, I meant that the
FPGA can be programmed at any one time with a single CPU type chosen
from a range of a dozen or so. I'm not trying to support multiple CPU
and 'SoC' types in a single Zephyr image at the same time. I'm looking
at a separate image for each one.


Re: Proposal to streamline GPIO, Pinmux driver API

Nashif, Anas
 

Hi,

Some time ago the TSC discussed APIs in general and it was agreed that we need to revisit the APIs as we have them right when there is critical mass of architecture and board support and I think we are getting there.

On Pinmux I agree it is low level and SOC specific, You have a very good story here that can be added to Jira.


Anas

On 2 Sep 2016, at 06:21, Piotr Mienkowski <Piotr.Mienkowski(a)schmid-telecom.ch> wrote:

Hello Community,

I would like to discuss GPIO / Pinmux driver combo which I believe become overcomplicated and may be confusing for a regular user.

The current API seems to be designed around Intel Quark architecture and QMSI SDK. In Quark there are separate Pinmux and GPIO modules and so we got separate Pinmux and GPIO drivers. However, in most chipsets GPIO module takes care of both PIO (reading/writing from/to a pin) and pin muxing (connecting pin to a peripheral/PIO controller). By now the functional split between the two drivers become blurred and is overlapping.

Some examples:

At present GPIO driver defines GPIO_PUD_PULL_UP (Enable GPIO pin pull-up) to be used with gpio_pin_configure() function and Pinmux driver has pinmux_pin_pullup() function. Both are meant to do the same thing however gpio_pin_configure() will not work with Intel Quark chips and pinmux_pin_pullup() will mostly not work with other chips e.g. Freescale/NXP FRDM-K64F. Still some chipsets e.g. Atmel SAM3x implement both functions but then even for Atmel SAM3x setting pin pull-down is only possible via gpio_pin_configure() function.

pinmux_pin_input_enable() function is used by Quark chips to disable/enable input pad and gpio_pin_configure() to set pin as input or output. This is not easily rendered from the function's name/description and in fact Atmel SAM3x driver implements pinmux_pin_input_enable() to configure pin as input or output overlapping it with the same functionality provided by gpio_pin_configure().

In case of ARM based chips e.g. Atmel SAM3x, Freescale/NXP FRDM-K64F to configure pin with pull-up and connect it to external peripheral one needs to call pinmux_pin_set() which takes as an argument pin index, e.g. pin PB2, third pin on port B would have index 34 and gpio_pin_configure() which takes as an argument port and port's pin number, e.g. PB2 has number 2. So in two subsequent calls we need to use different pin values even if we operate on the same pin. While this may be convenient for Quark chips it is not for other chip families.

Currently it is not really possible to know which function should be used when and how without analyzing Zephyr's source code.

I believe that split between Pinmux and GPIO driver is not a good general solution and in case we preserve the current API it will soon become even more convoluted.

I would like to propose to phase out Pinmux driver and implement pin multiplexing in GPIO driver. That would require adding something like GPIO_FUNC_A, ..., GPIO_FUNC_D to GPIO API.

Other possibility would be to limit Pinmux driver only to architectures that really need it, like Quark chips. Having pin multiplexing available simultaneously in GPIO and Pinmux driver will be confusing for Quark users, however that's already the case with pull-up configuration.

I haven't created a Jira issue, neither RFC in Gerrit yet. At first I would like to get a quick feedback if you find my arguments sensible.

Thanks,
Piotr


Re: How to handle a board with a dozen SoC's?

Jon Medhurst (Tixy) <tixy@...>
 

On Fri, 2016-09-02 at 15:46 +0100, Jon Medhurst (Tixy) wrote:
I'm trying to add Zephyr support for a board [1] where the 'SoC' is an
FPGA that can be programmed with a dozen different CPU types and varying
support IP, and I'm wondering how to organise this.
I realised this and $subject may be a bit ambiguous, I meant that the
FPGA can be programmed at any one time with a single CPU type chosen
from a range of a dozen or so. I'm not trying to support multiple CPU
and 'SoC' types in a single Zephyr image at the same time. I'm looking
at a separate image for each one.

--
Tixy


Daily Gerrit Digest

donotreply@...
 

NEW within last 24 hours:
- https://gerrit.zephyrproject.org/r/4472 : i2c: ksdk: Add shim driver
- https://gerrit.zephyrproject.org/r/4473 : i2c: Fix restart flag in burst read
- https://gerrit.zephyrproject.org/r/4491 : net: revert tcpip_poll_tcp() to not require a data_buf
- https://gerrit.zephyrproject.org/r/4490 : Bluetooth: UUID: Add 32bit UUID support
- https://gerrit.zephyrproject.org/r/4487 : Bluetooth: SDP: Server: Support service record registration
- https://gerrit.zephyrproject.org/r/4489 : Bluetooth: SDP: Server: Support ServiceAttrReq and ServiceSearchAttrReq
- https://gerrit.zephyrproject.org/r/4488 : Bluetooth: SDP: Server: Support ServiceSearchRequest
- https://gerrit.zephyrproject.org/r/4486 : Bluetooth: SDP: Server: Initialize and accept incoming connections
- https://gerrit.zephyrproject.org/r/4479 : Bluetooth: Controller: Measure and use correct stack size
- https://gerrit.zephyrproject.org/r/4485 : sample: fs: Add tests for fs_truncate and fs_statvfs
- https://gerrit.zephyrproject.org/r/4484 : drivers/pinmux: delete deprecated PINMUX_DEV_QUARK_MCU
- https://gerrit.zephyrproject.org/r/4483 : drivers/pinmux: fix CONFIG_PINMUX_DEV_NAME dependency issue
- https://gerrit.zephyrproject.org/r/4480 : fs: Add file system API to flush cache of an open file
- https://gerrit.zephyrproject.org/r/4478 : fs: Adds file system API to get volume statistics
- https://gerrit.zephyrproject.org/r/4477 : uart_qmsi: Get the interrupt handling right on ARC
- https://gerrit.zephyrproject.org/r/4474 : uart_console: Fix line endings
- https://gerrit.zephyrproject.org/r/4476 : samples/uart: More boards
- https://gerrit.zephyrproject.org/r/4475 : samples/drivers/uart: Fix line endings
- https://gerrit.zephyrproject.org/r/4471 : sanitycheck: allow extra arguments to be passed to the build

UPDATED within last 24 hours:
- https://gerrit.zephyrproject.org/r/4456 : net/ip: Fix warnings when enabling IP debugging
- https://gerrit.zephyrproject.org/r/4282 : net: fetch valid conn. to determine MSS in data_is_sent_and_acked()
- https://gerrit.zephyrproject.org/r/3934 : SDP Server
- https://gerrit.zephyrproject.org/r/4055 : Bluetooth: SDP: Server implementation
- https://gerrit.zephyrproject.org/r/3848 : lib: Introduce the CoAP implementation for Zephyr
- https://gerrit.zephyrproject.org/r/4372 : fs: Adds file system API to grow or shrink a file
- https://gerrit.zephyrproject.org/r/4139 : TCF: adds test fixed by ZEP-704
- https://gerrit.zephyrproject.org/r/4371 : win-build: fixes to build with alternative make implementations
- https://gerrit.zephyrproject.org/r/3313 : samples/drivers/crypto: crypto sample app
- https://gerrit.zephyrproject.org/r/3312 : drivers/crypto: Tinycrypt shim driver
- https://gerrit.zephyrproject.org/r/4461 : i2c: qmsi_shim: change some i2c config parameters to SoC specific
- https://gerrit.zephyrproject.org/r/4360 : ksdk: Add KSDK RNGA driver.
- https://gerrit.zephyrproject.org/r/4445 : ksdk: Build ksdk fsl_enet.c and fsl_phy.c
- https://gerrit.zephyrproject.org/r/4165 : net: drivers: Add a fake ieee802154 radio driver for qemu
- https://gerrit.zephyrproject.org/r/3924 : lib/http: Add test-case
- https://gerrit.zephyrproject.org/r/4457 : DONT MERGE
- https://gerrit.zephyrproject.org/r/4460 : kconfig: include configuration fragment files from output directory

MERGED within last 24 hours:
- https://gerrit.zephyrproject.org/r/4470 : Only build nav.yaml if docs successfully built
- https://gerrit.zephyrproject.org/r/4415 : Bluetooth: HoG: Require authentication for connections
- https://gerrit.zephyrproject.org/r/4414 : Bluetooth: Add sample implementing HIDS
- https://gerrit.zephyrproject.org/r/4413 : Bluetooth: Add service sample for HoG
- https://gerrit.zephyrproject.org/r/4469 : Bluetooth: btp: Extend BTP specification to cover L2CAP tests


How to handle a board with a dozen SoC's?

Jon Medhurst (Tixy) <tixy@...>
 

Hi

I'm trying to add Zephyr support for a board [1] where the 'SoC' is an
FPGA that can be programmed with a dozen different CPU types and varying
support IP, and I'm wondering how to organise this.

[1] https://www.arm.com/products/tools/development-boards/versatile-express/cortex-m-prototyping-system.php

It seems to me that 'BOARD' is what the build system expects to use to
specify the thing to build, but adding a dozen new boards under /boards
(one for each 'SoC') doesn't seem the right way to go - and I would then
need somewhere to put the common code for the physical board.

I'm going to be in a similar situation for creating my dozen or so SoC's
but I believe that the build system may be a bit more flexible in that
situation, with SOC_FAMILY and SOC_SERIES.

As well as the hardware board there is a host of software simulations
[2] for similar but differing configurations as the hardware. I don't
believe that adds any extra complexity though, apart from the number of
ever expanding versions and them not being definitively identified by
name or number. Oh joy...

[2] https://developer.arm.com/docs/dui0837/latest/programming-reference-for-mps2-fvps/mps2-about

Thanks for any advice.

--
Tixy


Re: Porting to Cortex-M0+

Piotr Mienkowski <Piotr.Mienkowski@...>
 

Hi Maureen,

Another member of the TSC will follow up with Atmel.
Thanks, I will wait for the green light. My Atmel SAM E70 port works well in my local workarea, I have everything necessary for initial support apart from UART driver. There are still a few minor implementation details I'll have to discuss but I'll do it later in a separate thread when I know I am supposed to work on it.

I have one more question to the design flow I could not find a clear answer in the wiki to. As I have mentioned I would like to add support for Atmel SAM E70 chipset, I've already opened a Jira issue. I expect that now before doing the actual job and especially before trying to push anything to Gerrit I need to wait until the task is officially accepted and assigned to me, isn't it?

Cheers,
Piotr


Re: having trouble getting the echo client to work using TCP/uIP on K64F

Rohit Grover
 

Paul, Jukka,

> On Thu, 1 Sep 2016 14:47:41 +0000
> Rohit Grover <Rohit.Grover(a)arm.com> wrote:
>
> > Jukka, Paul,
> >
> > I believe we should go ahead and fix tcpip_poll_tcp() according to the
> > patch I submitted previously. This fix can supersede
> > https://gerrit.zephyrproject.org/r/#/c/4226, and we can pause on that
> > particular pull request for now.
>
> +1. Would you submit it to Gerrit?
>

Submitted https://gerrit.zephyrproject.org/r/#/c/4491/

Regards,
Rohit.
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.


Re: Request to have generic sensor support

Davidoaia, Bogdan M <bogdan.m.davidoaia@...>
 

Hello Kasim,

The sensor types from sensor.h are in no way final, and new types can be
added as the need arises for new drivers.

Not sure if your driver could define a more specific type (that may be
useful for other future drivers) rather then a generic one, but a
generic data type can be easily added.

For sending generic data to the driver, you can add a
SENSOR_ATTR_USER_DATA attribute, a SENSOR_VALUE_TYPE_USER_DATA value
type and a void *user_data field in the union from struct sensor_value.

Sending generic data back to the application can be done by adding a
SENSOR_CHAN_USER_DATA channel (together with the generic sensor value
type and filed).

Best regards,
Bogdan

On Jo, 2016-09-01 at 14:19 +0000, kasim shibi wrote:


Hi All,


I happened to work on a sensor
driver in zephyr 1.4. The
"sensor.h" provides support for
very few sensors.
Moreover lack of support for any
custom/generic data to pass between
the application and driver.
Please correct me if i am wrong.

I am looking for an option to pass
an array (1024 bytes), where the
internal data format i can
define/manage between my driver and
application.


If at all , only choice is to add
as a new sensor. Please share the
steps for the zephyr team to add
support for a new sensor.


Thanks
Kasim




Proposal to streamline GPIO, Pinmux driver API

Piotr Mienkowski <Piotr.Mienkowski@...>
 

Hello Community,

I would like to discuss GPIO / Pinmux driver combo which I believe become overcomplicated and may be confusing for a regular user.

The current API seems to be designed around Intel Quark architecture and QMSI SDK. In Quark there are separate Pinmux and GPIO modules and so we got separate Pinmux and GPIO drivers. However, in most chipsets GPIO module takes care of both PIO (reading/writing from/to a pin) and pin muxing (connecting pin to a peripheral/PIO controller). By now the functional split between the two drivers become blurred and is overlapping.

Some examples:

At present GPIO driver defines GPIO_PUD_PULL_UP (Enable GPIO pin pull-up) to be used with gpio_pin_configure() function and Pinmux driver has pinmux_pin_pullup() function. Both are meant to do the same thing however gpio_pin_configure() will not work with Intel Quark chips and pinmux_pin_pullup() will mostly not work with other chips e.g. Freescale/NXP FRDM-K64F. Still some chipsets e.g. Atmel SAM3x implement both functions but then even for Atmel SAM3x setting pin pull-down is only possible via gpio_pin_configure() function.

pinmux_pin_input_enable() function is used by Quark chips to disable/enable input pad and gpio_pin_configure() to set pin as input or output. This is not easily rendered from the function's name/description and in fact Atmel SAM3x driver implements pinmux_pin_input_enable() to configure pin as input or output overlapping it with the same functionality provided by gpio_pin_configure().

In case of ARM based chips e.g. Atmel SAM3x, Freescale/NXP FRDM-K64F to configure pin with pull-up and connect it to external peripheral one needs to call pinmux_pin_set() which takes as an argument pin index, e.g. pin PB2, third pin on port B would have index 34 and gpio_pin_configure() which takes as an argument port and port's pin number, e.g. PB2 has number 2. So in two subsequent calls we need to use different pin values even if we operate on the same pin. While this may be convenient for Quark chips it is not for other chip families.

Currently it is not really possible to know which function should be used when and how without analyzing Zephyr's source code.

I believe that split between Pinmux and GPIO driver is not a good general solution and in case we preserve the current API it will soon become even more convoluted.

I would like to propose to phase out Pinmux driver and implement pin multiplexing in GPIO driver. That would require adding something like GPIO_FUNC_A, ..., GPIO_FUNC_D to GPIO API.

Other possibility would be to limit Pinmux driver only to architectures that really need it, like Quark chips. Having pin multiplexing available simultaneously in GPIO and Pinmux driver will be confusing for Quark users, however that's already the case with pull-up configuration.

I haven't created a Jira issue, neither RFC in Gerrit yet. At first I would like to get a quick feedback if you find my arguments sensible.

Thanks,
Piotr


Re: having trouble getting the echo client to work using TCP/uIP on K64F

Paul Sokolovsky
 

On Thu, 1 Sep 2016 14:47:41 +0000
Rohit Grover <Rohit.Grover(a)arm.com> wrote:

Jukka, Paul,

I believe we should go ahead and fix tcpip_poll_tcp() according to
the patch I submitted previously. This fix can supersede
https://gerrit.zephyrproject.org/r/#/c/4226, and we can pause on that
particular pull request for now.
+1. Would you submit it to Gerrit?

We should also avoid regressing on
any IPv6 functionality, so if there are tests we could use to
evaluate IPv6 then we should employ them to validate changes to
tcpip_poll_tcp().
I believe running echo_server/echo_client should be a good first step,
I'll look into that.


Fixing tcpip_poll_tcp() isn't the complete answer. With changes to
tcpip_poll_tcp(), I can get simple request-response transactions, but
sustained/multiple transactions don't work; so there is still reason
to suspect that TCP support is unreliable.
As I mentioned, multiple (well, up to 5-6) packets work for me with
QEMU. I'll try it with FRDM-K64F Ethernet driver soon.

The bigger problem appears to be that the uIP port for Z has grown
unmaintainable. I can sympathize with Jukka when he says that TCP
support on uIP "is very cryptic and difficult to follow." It is not
clear to me if uIP is tricky to port in general, or that Z poses a
special challenge. Does Zephyr intend to switch from uIP to YAIP? If
so, then perhaps one strategy would be to wait for YAIP to catch up.
If Zephyr wishes to maintain support for TCP/uIP, then someone needs
to take a fresh look at the current uIP port, possibly from the point
of view of a porter of uIP.
My understanding is that yes, YAIP is intended to replace IP stack
implementation in Z, though maybe exact timeline isn't known yet. My
current task is to prepare a proof-of-concept demo of a scripting
language running on top of Zephyr, so I'd be interested to follow route
of trying to fix up the current uIP implementation, though probably not
go too deep with that.


Regards,
Rohit.

--
Best Regards,
Paul

Linaro.org | Open source software for ARM SoCs
Follow Linaro: http://www.facebook.com/pages/Linaro
http://twitter.com/#!/linaroorg - http://www.linaro.org/linaro-blog


Re: having trouble getting the echo client to work using TCP/uIP on K64F

Paul Sokolovsky
 

Hello,

On Thu, 01 Sep 2016 11:11:15 +0300
Jukka Rissanen <jukka.rissanen(a)linux.intel.com> wrote:

[]

Still, that commit was made in
https://gerrit.zephyrproject.org/r/gitweb?p=zephyr.git;a=commitdiff;h
=61edc68c9ecf221d18acc8037d541f5d79eee3c7 ,
with description 
"net: tcp: Supporting TCP client functionality when using IPv6". I
don't know if something in IPv6 warrants changes to tcpip_poll_tcp()
done in that commit, I guess only Jukka can tell. But the issue in
Unfortunately I do not remember why I changed tcpip_poll_tcp(), the
uIP code (and especially TCP support) is very cryptic and difficult to
follow. One basically needs to run the stack and see how it behaves.
I see. It seems that one of the biggest changes done was to convert
single static packet buffer design on uIP to support multiple buffers.
Ironically, that's what another Contiki-originated IP stack (or at
least IP stack from the same author, Adam Dunkels) - lwIP - does. It
supports multiple in-flight packet buffers, clearer API, better
performance. I wonder if using it might have been better choice for
Zephyr. All the above comes at the expense of doubling (or more) of
code size, so maybe not still.

Anyway, with Z's own new IP stack in progress, that's more of
speculation, I guess focus should be on stabilizing current uIP based
implementation, until the new stack reaches needed functionality level.


--
Best Regards,
Paul

Linaro.org | Open source software for ARM SoCs
Follow Linaro: http://www.facebook.com/pages/Linaro
http://twitter.com/#!/linaroorg - http://www.linaro.org/linaro-blog


Re: Porting to Cortex-M0+

Maureen Helm
 

Hi Piotr,

-----Original Message-----
From: Piotr Mienkowski [mailto:Piotr.Mienkowski(a)schmid-telecom.ch]
Sent: Wednesday, August 31, 2016 8:09 AM
To: devel(a)lists.zephyrproject.org
Subject: [devel] Re: Re: Re: Re: Re: Re: Porting to Cortex-M0+

Hi Maureen,

Thanks for all the explanations. I've created a Jira issue to add support for
Atmel SAM E70 family. If it's approved I can work on it.
https://jira.zephyrproject.org/browse/ZEP-759

by the NXP ksdk and Nordic mdk. As far as folder structure goes, I
think anything under ext/hal/asf (or whatever we end up calling it) has some
freedom to do what makes sense.
I am actually more in favor of giving subfolders company names (currently the
style is mixed). The main reason being the fact that the various names of SDKs
tend to be cryptic so user may have trouble finding what he is looking for. Also
companies, once every few years, tend to change these names so acronyms
such as ksdk, qmsi, asf may one day get outdated.

For ext/hal/cmsis and ext/hal/ksdk, I tried to preserve the structure
from the original
I am too very much for preserving the structure of the original SDK

IANAL either, but will check with someone at LF on this.
You've mentioned in the post below that Zephyr TSC has to ask the governing
board to approve the ASF license. What should we do to trigger this?
I brought this to the TSC yesterday, and the decision was to first ask Atmel if they can change to a standard license already approved by the Zephyr governing board. Another member of the TSC will follow up with Atmel.


Daily JIRA Digest

donotreply@...
 

NEW JIRA items within last 24 hours: 4
[ZEP-760] Clean up samples and sanitise them.
https://jira.zephyrproject.org/browse/ZEP-760

[ZEP-759] Add preliminary support for Atmel SAM E70 (Cortex-M7) chipset family and SAM E70 Xplained board
https://jira.zephyrproject.org/browse/ZEP-759

[ZEP-756] Remove Sandboxes from documentation
https://jira.zephyrproject.org/browse/ZEP-756

[ZEP-757] tests/kernel/test_context/ fail in Arduino 101 and Quark SE C1000
https://jira.zephyrproject.org/browse/ZEP-757


UPDATED JIRA items within last 24 hours: 5
[ZEP-750] Arduino 101 board should support one configuration using original bootloader
https://jira.zephyrproject.org/browse/ZEP-750

[ZEP-244] Multiple Published Versions Support
https://jira.zephyrproject.org/browse/ZEP-244

[ZEP-758] Rename Quark SE Devboard to its official name: Quark SE C1000
https://jira.zephyrproject.org/browse/ZEP-758

[ZEP-233] Support USB mass storage device class
https://jira.zephyrproject.org/browse/ZEP-233

[ZEP-346] Provide a HTTP library within Zephyr
https://jira.zephyrproject.org/browse/ZEP-346


CLOSED JIRA items within last 24 hours: 5
[ZEP-210] (Duplicate) Zephyr TEE compatibility
https://jira.zephyrproject.org/browse/ZEP-210

[ZEP-238] (Fixed) Usage of ARCH in application Makefiles is misleading
https://jira.zephyrproject.org/browse/ZEP-238

[ZEP-711] (Fixed) I2c: fails to write with mode fast plus
https://jira.zephyrproject.org/browse/ZEP-711

[ZEP-528] (Fixed) ARC has 2 almost identical copies of the linker script
https://jira.zephyrproject.org/browse/ZEP-528

[ZEP-754] (Duplicate) Remove the need to specify ARCH in the command line
https://jira.zephyrproject.org/browse/ZEP-754


RESOLVED JIRA items within last 24 hours: 1
[ZEP-715] (Fixed) Add K64F clock configurations
https://jira.zephyrproject.org/browse/ZEP-715

6821 - 6840 of 8189