Cancelled: Zephyr Project: Dev Meeting

This event has been cancelled.

When:
Thursday, 29 April 2021
3:00pm to 4:00pm
(UTC+00:00) UTC

Where:
Microsoft Teams Meeting

Organizer: devel@...

Description:

Hi; sorry for the short notice, but Dev-review is cancelled for today.

Kumar is on vacation (which is why I sent the agenda) and I've been
informed that today's dev-review conflicts with talk selection for the
Zephyr Developer summit, so our usual suspects from the TSC will be
unable to attend. Let's pick up next week.

Martí

"Bolivar, Marti via lists.zephyrproject.org"
<marti.bolivar=nordicsemi.no@...> writes:

Reminder: Zephyr Project: Dev Meeting

When: Thursday, 29 April 2021, 3:00pm to 4:00pm, (GMT+00:00) UTC

Where:Microsoft Teams Meeting

An RSVP is requested. Click here to RSVP

Organizer: devel@...

Description:

Here's the agenda topics for this week:

Setup MPU for code relocated to SRAM
-
https://github.com/zephyrproject-rtos/zephyr/pull/34086

* Any topics anyone else has.

Cancelled: Zephyr: Toolchain Working Group

This event has been cancelled.

When:
Monday, 3 May 2021
3:00pm to 4:00pm
(UTC+00:00) UTC

Where:
Microsoft Teams Meeting

Organizer: Torsten Rasmussen

Description:

[I may have posted this in the wrong group, so I've also raised it in Zephyr Users.]

I'm new to Zephyr and am trying to get a Linux VM hosted native_posix unit test build environment set up for our Zephyr nRF52 embedded project. 

I've set up the Zephyr SDK and west native_posix (& qemu_x86) build environment and can build and run the samples and a simple hello world test under my Ubuntu 20.04 Linux VM.

We'd like to use GoogleTest/Mock for our unit test environment within the Zephyr native_posix environment. Has anyone here got that working? I've got some way following this StackOverflow post unit-testing-c-code-into-zephyr-with-googletest , but unfortunately it does not provide details of the module.yml and Kconfig file contents. I don't yet know enough to fill them in myself and west / cmake reports that my googletest module is "not a valid zephyr module".

Any help or pointers would be appreciated!

Hey Keith,

Thanks for the lead. This certainly helps. I still have some
questions, hope that's ok.

Lets say I'm describing the bytes that relate to gpio controller A:

```
gpioa: gpio@40010000 {
compatible = "ambiq,apollo3-gpio";
gpio-controller;
reg = <0x40010000 4 /* PADREG */
0x40010040 2 /* CFGA */
0x400100e0 4 /* ALTPADCFGA */
0x40010080 1 /* RDA (input read) */
0x40010088 1 /* WTA (output write) */
0x40010090 1 /* WTSA (output set) */
0x40010098 1 /* WTCA (clear) */
0x400100a0 1 /* ENA (enable) */
0x400100a8 1 /* ENSA (set) */
0x400100b4 1 /* ENCA (clear) */
>;
ngpios = <4>;
label = "GPIOA";
#gpio-cells = <2>;
};
```

RDA register is an input register to read the input state of the first
32 pins. RDB register holds the input state of the next 18 pins.
How would I describe that in this gpio controller? Do I describe
specific pins at this stage or is that the register I specify,
combined
with its size, should include all the bytes that refer to the
controlled pins? Meaning that this memory description can include more
than just bits referring to the pins connected to the gpio controller
A and more specific pin description happens in another node.
So the aforementioned RDA register is described here with its address
and size of 32bits. That memory range 0x40010080 - 0x40010081
describes a register that is used by 32 pins.

Another example is the ALTPADCFGA. It describes 32 pins using 4 32bits
registers. Should I specify its size as 4 (entire register) or
only 1 as the first byte of that register is the only one that
references gpio controller A.

I guess my problems come from the lack of understanding what exactly
am I describing here.

Thanks again,
Michal



On Mon, Apr 26, 2021 at 10:29 PM Keith Short <keithshort@...> wrote:

The GPIO driver for the ITE IT8xxx2 family also interleaves the register space.

You could follow the model used for that driver - create multiple reg phandles for the individual registers.

https://github.com/zephyrproject-rtos/zephyr/blob/a3469a04978540b1d1cf0173bc557aeb9c0453be/dts/riscv/it8xxx2.dtsi#L93

Keith

On Sun, Apr 25, 2021 at 4:19 PM <ciesielskimm@...> wrote:

Hello,

I'm trying to add support for the Ambiq Apollo series chips. I'm new to the Zephyr and not very experienced with Device Tree format.
Currently I'm working on the zephyr/dts/arm/ambiq/apollo.dtsi. I'm trying to add the GPIO control registers. I'm modyfing
the STM32 dtsi file. STM32's define the GPIO control in a different way. All the Pad A registers are defined in a continous memory block.
In Ambiq SOCs those they are interleaved. The image below shows the memory map.



First its the Pad configuration registers. Then its GPIO configuration register. I'm wondering how should I implement this
memory layout in the dtsi.

Reminder: Zephyr Project: APIs

When: Tuesday, 27 April 2021, 4:00pm to 5:00pm, (GMT+00:00) UTC

Where:Microsoft Teams Meeting

An RSVP is requested. Click here to RSVP

Organizer: devel@...

Description:

Hi,

This is a reminder that the v2.6.0 merge window for new features closes this Friday, 7th of May. After that, only bug fixes and documentation will be merged until the final release is tagged, which is targeted for Friday, May 28th. Exceptions require TSC approval. New feature PRs may still be submitted while the merge window is closed, but please keep in mind that maintainers will have less time to review them during the release stabilization period.

Please add the v2.6.0 milestone to PRs that need to be included in the release, and do not wait until Friday, May 7th to submit them.

https://github.com/zephyrproject-rtos/zephyr/wiki/Program-Management
https://github.com/zephyrproject-rtos/zephyr/pulls?q=is%3Apr+is%3Aopen+sort%3Aupdated-desc+milestone%3Av2.6.0

Please try to help fix bugs, test release candidates, and write release notes to minimize the time the merge window is closed so we can all quickly get back to adding fun new things to Zephyr!

Thank you for your contributions!

- k

Hi all,

Items for today:

- Pinctrl
- Issue: https://github.com/zephyrproject-rtos/zephyr/issues/22748

If you have additional items please let me know.

Teams link: https://teams.microsoft.com/l/meetup-join/19%3ameeting_NWU2MjZlYWEtZDcwMi00MWQzLTgwMjEtNDdkYjQwMjBjMmFj%40thread.v2/0?context=%7b%22Tid%22%3a%22af0096d9-700c-411a-b795-b3dd7122bad2%22%2c%22Oid%22%3a%22841a7c92-7816-4faf-9887-5e334e88f6d8%22%7d

https://lists.zephyrproject.org/g/devel/calendar
https://github.com/zephyrproject-rtos/zephyr/projects/18

Minutes:
https://docs.google.com/document/d/1lv-8B5QE2m4FjBcvfqAXFIgQfW5oz6306zJ7GIZIWCk/edit#

Regards,

Carles

Reminder: Zephyr Memory Footprint - biweekly discussion

When: Monday, 26 April 2021, 3:00pm to 4:00pm, (GMT+00:00) UTC

Where:Microsoft Teams Meeting

An RSVP is requested. Click here to RSVP

Organizer: devel@...

Description: Working doc: https://docs.google.com/document/d/1bnQLJKVhgI3zkk3MsSXun8onEsA8z1Rf5ohdbCHASmU/edit#heading=h.x36xe8bnwr9r

Hello,

I'm trying to add support for the Ambiq Apollo series chips. I'm new to the Zephyr and not very experienced with Device Tree format.
Currently I'm working on the zephyr/dts/arm/ambiq/apollo.dtsi. I'm trying to add the GPIO control registers. I'm modyfing
the STM32 dtsi file. STM32's define the GPIO control in a different way. All the Pad A registers are defined in a continous memory block.
In Ambiq SOCs those they are interleaved. The image below shows the memory map.



First its the Pad configuration registers. Then its GPIO configuration register. I'm wondering how should I implement this
memory layout in the dtsi.

Adding the list back in Cc.

"Theo Hussey via Lists.Zephyrproject.Org"
<theo=open-cosmos.com@...> writes:

Thank you for your detailed response, I tried to use the binding you
suggested but I was not sure where to put it as I developing the
driver out of tree.

I meant that binding as an example, not as something to copy/paste --
for a different IP block you will need your own binding.

I switched to developing the driver in tree instead and was able to
get the driver working after setting up the binding correctly and
fixing some typos with the macros in my driver.

You can put the binding in a dts/bindings subdirectory of anything in
your DTS_ROOT cmake variable or any Zephyr module that declares itself a
dts-root, like modules/hal/nxp/zephyr/module.yml and
modules/hal/stm32/zephyr/module.yml do.

Thanks

Theo

Sorry for the late cancelation. Not feeling well and there wasn’t much of an agenda this week.

Cancelled: Zephyr Project: Dev Meeting

This event has been cancelled.

When:
Thursday, 22 April 2021
3:00pm to 4:00pm
(UTC+00:00) UTC

Where:
Microsoft Teams Meeting

Organizer: devel@...

Description:

Hi Theo,

"Theo Hussey via lists.zephyrproject.org"
<theo=open-cosmos.com@...> writes:

Hi,

I am trying to develop an out of tree QSPI driver for the ATSAME51 micro controller.

I have added my entries to the device tree:

soc {
qspi0 : qspi@42003400 {
compatible = "atmel,sam0-qspi" ;
reg = < 0x42003400 0x40 >;
interrupts = < 134 0 >;
status = "okay" ;
label = "QSPI_0" ;
clocks = < &mclk 0x10 13 >, < &mclk 0x10 21 >, < &mclk 0x1C 13 >;
clock-names = "QSPI_AHB_Clock" , "QSPI_2X_AHB_Clock" , "QSPI_APB_Clock" ;
#address-cells = < 1 >;
#size-cells = < 0 >;
};
};
};

There is an extra unmatched "};" here. I'm assuming that is just a
copy/paste issue in this email? It looks like a syntax error.

&qspi0 {
gd25q16 : gd25q16c@0 {
compatible = "jedec,spi-nor" ;
label = "GD25Q16C" ;
reg = < 0 >;
spi-max-frequency = < 80000000 >;
size = < 0x200000 >;
has-be32k;
has-dpd;
t-enter-dpd = < 20000 >;
t-exit-dpd = < 100000 >;
jedec-id = [c8 40 15] ;
};
};

But I receive the following errors when trying to build, in comparison if I add the nor flash as an child of a sercom spi peripheral it builds fine. Does anyone have any suggestions on what could be causing this?

[snip]

zephyr/include/generated/devicetree_unfixed.h:4014:35: error: 'DT_N_S_soc_S_qspi_42003400_S_gd25q16c_0_BUS_P_label' undeclared (first use in this function); did you mean 'DT_N_S_soc_S_qspi_42003400_S_gd25q16c_0_P_label'?

I'm going to explain what this mess means for the sake of the list
archives before getting to what I am guessing the problem is.

'DT_N_S_soc_S_qspi_42003400_S_gd25q16c_0_BUS_P_label'

The 'DT_N_S_soc_S_qspi_42003400_S_gd25q16c_0' part is the 'node
identifier' for the gd25q16c@0 node.

'Node identifiers' are introduced here:

https://docs.zephyrproject.org/latest/guides/dts/api-usage.html#node-identifiers

The secret decoder ring for unpacking node identifiers is:

- 'DT_N' -> 'devicetree node'
- '_S_' -> '/'
- all special characters become '_'

So that:

DT_N_S_soc_S_qspi_42003400_S_gd25q16c_0_BUS_P_label

becomes:

devicetree node /soc/qspi@42003400/gd25q16c@0 _BUS_P_label

The trailing '_BUS_P_label' is just the devicetree API trying to figure
out what the 'label' property of the bus node for
/soc/qspi@42003400/gd25q16c@0 is.

I also see:

- 'qspi@42003400' does have a label property in your DTS, "QSPI_0"
- its compatible, 'atmel,sam0-qspi', is not upstream

So I'm guessing that the problem is:

- you've got a custom binding for 'atmel,sam0-qspi',
- it is a missing a 'bus: qspi' line

Example binding with a 'bus: qspi' line:

https://github.com/zephyrproject-rtos/zephyr/blob/master/dts/bindings/qspi/st%2Cstm32-qspi.yaml#L23

If that line is missing, please add it and try again.

Otherwise please provide more details on your binding.

Thanks and HTH,
Martí