Alright, so thanks to Nick (thank you!) I have now narrowed down my problem a little.

as a background, here is the C code that is causing the issue (i marked the error-origin in fat characters):

#define LIS3DHH_SPI_CFG(inst)                         \
    (&(struct lis3dhh_spi_cfg){                       \
        .spi_conf = {                                 \
            .frequency =                              \
              DT_INST_PROP(inst, clock_frequency),  \
            .operation = (SPI_WORD_SET(8) |           \
                          SPI_OP_MODE_MASTER |        \
                          SPI_MODE_CPOL |             \
                          SPI_MODE_CPHA),             \
            .slave = DT_INST_REG_ADDR(inst),          \
            .cs = LIS3DHH_SPI_CS_PTR(inst),           \
        },                                            \
        .cs_gpios_label = LIS3DHH_SPI_CS_LABEL(inst), \
    })


So the problem is the devicetree that i am trying to use. Nick suggested i move the "spi-max-frequency" from the lis3dhh device to the spi2 node (like the spi yaml file suggests -> dts/bindings/spi/spi-device.yaml). So something like this:

&spi2 {
    pinctrl-0 = <&spi2_sck_pb13 &spi2_miso_pb14 &spi2_mosi_pb15>;/*PIN34,PIN35,PIN36*/
    cs-gpios = <&gpioc 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;/* PC6, Acc_CS */
    status = "okay";
    spi-max-frequency = <10000000>; /*max. 10MHz*/
 
    lis3dhh: lis3dhh@11 {
        compatible = "st,lis3dhh","st,spi_lis3dhh";
        reg = <0x11>;
        label = "LIS3DHH";
        int1-gpios = <&gpioc 7 GPIO_ACTIVE_HIGH>; /*PC7*/
        int2-gpios = <&gpioc 8 GPIO_ACTIVE_HIGH>;  /*PC8 */
    };
};


However, this lead me to realize that my devicetree does not access the normal spi-device.yaml but rather the st,stm32-spi.yaml which is accessing  st,stm32-spi-common.yaml .
Now this file is not actually demanding a "spi-max-frequency" value at all. Though spi-controller.yaml it is possible to assign it a clock-frequency though.

So what I have tried now is adding that clock-frequency in both my code and in the devicetree. Now when i try that, i get the following error (i tried both options of adding it under the lis3dhh device and the spi node):

/home/markus/driver_test_lis3dhh/my-workspace/iots-fiso-id-p2-zephyr/build/zephyr/include/generated/devicetree_unfixed.h:24461:36: error: 'DT_N_S_soc_S_spi_40003800_S_lis3dhh_11_P_clock_frequency' undeclared here (not in a function); did you mean 'DT_N_S_soc_S_spi_40003800_S_lis3dhh_11_P_compatible'?
24461 | #define DT_N_INST_0_st_lis3dhh     DT_N_S_soc_S_spi_40003800_S_lis3dhh_11

I also tried editing st,stm32-spi-common.yaml to include an spi-max-frequency value.
Here I get the following error:

/home/markus/driver_test_lis3dhh/my-workspace/iots-fiso-id-p2-zephyr/build/zephyr/include/generated/devicetree_unfixed.h:24461:36: error: 'DT_N_S_soc_S_spi_40003800_S_lis3dhh_11_P_spi_max_frequency' undeclared here (not in a function); did you mean 'DT_N_S_soc_S_spi_40003800_P_spi_max_frequency'?
24461 | #define DT_N_INST_0_st_lis3dhh     DT_N_S_soc_S_spi_40003800_S_lis3dhh_11

So I guess there is an issue with me trying to access the wrong level of the devicetree? If I understand the error correctly, it is telling me that I am trying to access spi-max-frequency on the lis3dhh device (which i also gave that attribute by the way) but that does not exist and I should rather address the spi node's spi-max-frequency.
Now I don't really understand how I change this. Either accessing the node's spi-max-frequency or how to tell the devicetree to use the lis3dhh's spi-max-frequency attribute.


Again, I am very thankful for any advice.
Cheers,
Markus

1. A single I2C bus
2. TCA6418
3. Enable other regulators and wait a bit
4. All other external devices, including other devices on the I2C bus.

Is it possible to do this using just the priority levels in the drivers?

For legacy reasons we're using Zephyr v2.3.0 and are unlikely to be able to upgrade to a newer version any time soon.

Thanks,

Glenn

Reminder: Zephyr Project: Dev Meeting

When:
09/09/2021
3:00pm to 4:00pm
(UTC+00:00) UTC

Where:
Microsoft Teams Meeting

Organizer: devel@...

An RSVP is requested. Click here to RSVP

Description:

On 2021/09/08 16:22, Yasushi SHOJI wrote:

On Wed, Sep 8, 2021 at 10:23 AM Katsuhiro Suzuki <katsuhiro@katsuster.net> wrote:
Why do you `use _current_cpu` at all? `_arch_switch()` or
`arch_switch()` on the main branch takes
both new and old thread handles.

Because to keep consistency for another context switching (by preemption) and
other interrupts.
Only _current_cpu.current is available when an interrupt occurred.

RISC-V's FPU arch has the flag to permit/forbid using FPU. In Zephyr, this flag is set to
forbid side if thread was declared as not using FPU. And CPU raise interrupt when using
any FPU instruction at FPU forbidden state.

Katsuhiro Suzuki wrote:

Newer switching sets NEW thread handle into _current_cpu.current
BEFORE calling arch_switch().  This implementation will face a
problem in RISC-V environment if thread calls do_swap() explicitly
and switch to thread B (use FPU) from thread A (not use FPU)
because...

So... this is the very middle of a context switch.  The expectation of the kernel is that no exception/interrupt handlers are going to fire, because (by definition) if they do they will see corrupt/inconsistent thread state.  Or rather, if an architecture wants to allow that, it needs to be prepared to do the work.
I mean, the information is available to you: you know what the new thread is, because you're handed its switch handle which you created yourself.  You likewise know the old thread, because you're passed the address of its switch_handle field from which you can extract a pointer to the enclosing thread struct.  You know you're in the middle of a context switch, because arch_switch() was called.  You COULD write an FPU exception handler to detect this state and do the right thing.  I don't necessarily think this would be a good design, but it's possible.

Can you explain why you need to take an FPU exception in the middle of a context switch?  That seems a little questionable to me.  Why are you hitting lazy-saved FPU registers in a situation where it would be faster to just check the mask state to see if they are populated or not?  (Forgive me: I don't know the RISC-V FPU architecture, but I assume that's the situation you're in: the FPU registers may or may not be in use and using them if they aren't will trap.)

Andy

Hi,
On Wed, Sep 8, 2021 at 10:23 AM Katsuhiro Suzuki
<katsuhiro@katsuster.net> wrote:

I have question about newer version of context switching (CONFIG_USE_SWITCH=y).

Does RISC-V support USE_SWITCH?

Newer switching sets NEW thread handle into _current_cpu.current BEFORE calling arch_switch().
This implementation will face a problem in RISC-V environment if thread calls do_swap() explicitly and switch to thread B (use FPU) from thread A (not use FPU) because...

AFAICS, even with v1.11, we are setting `_current` to `new_thread` in
`_Swap()` before calling `_arch_switch()`.
What version are you referring to as "older"?

Why do you `use _current_cpu` at all? `_arch_switch()` or
`arch_switch()` on the main branch takes
both new and old thread handles.

Best,

I have question about newer version of context switching (CONFIG_USE_SWITCH=y).

Newer switching sets NEW thread handle into _current_cpu.current BEFORE calling arch_switch().
This implementation will face a problem in RISC-V environment if thread calls do_swap() explicitly and switch to thread B (use FPU) from thread A (not use FPU) because...

Reminder: Zephyr Project: APIs

When:
09/07/2021
4:00pm to 5:00pm
(UTC+00:00) UTC

Where:
Microsoft Teams Meeting

Organizer: devel@...

An RSVP is requested. Click here to RSVP

Description:

Cancelled: Zephyr: Networking Forum

This event has been cancelled.

When:
Tuesday, September 7, 2021
3:00pm to 4:00pm
(UTC+00:00) UTC

Where:
Microsoft Teams Meeting

Organizer: tsc@...

Description:

Reminder: Zephyr: Networking Forum

When:
09/07/2021
3:00pm to 4:00pm
(UTC+00:00) UTC

Where:
Microsoft Teams Meeting

Organizer: tsc@...

An RSVP is requested. Click here to RSVP

Description:

Hi everyone

I am currently trying to write a driver for an STMicroelectronics LIS3DHH accelerometer. I based my code on the existing LIS2DH code that is already integrated in Zephyr and tried to adapt it to the LIS3DHH. Now when I try to build my project I get an error that i can't quite figure out where it is coming or originating from since it is occurring in an automatically generated file:

from /home/markus/driver_test_lis3dhh/my-workspace/zephyr/drivers/sensor/spi_lis3dhh/lis3dhh.c:7:
/home/markus/driver_test_lis3dhh/my-workspace/iots-fiso-id-p2-zephyr/build/zephyr/include/generated/devicetree_unfixed.h:24457:36: error: 'DT_N_S_soc_S_spi_40003800_S_lis3dhh_11_P_spi_max_frequency' undeclared here (not in a function); did you mean 'DT_N_S_soc_S_spi_40003800_S_lis3dhh_11_P_compatible_IDX_0'?
24457 | #define DT_N_INST_0_st_lis3dhh     DT_N_S_soc_S_spi_40003800_S_lis3dhh_11

I guess it looks like it is coming from the devicetree, but I can't see anything wrong with that one. I am doing all this on a custom board, so the devicetree I wrote myself - so I guess chances are high I did something wrong there, but I don't know what it could be.

So here is the relevant part of my devicetree if that helps:

&spi2 {
    pinctrl-0 = <&spi2_sck_pb13 &spi2_miso_pb14 &spi2_mosi_pb15>;/*PIN34,PIN35,PIN36*/
    cs-gpios = <&gpioc 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;/* PC6, Acc_CS */
    status = "okay";
 
    lis3dhh: lis3dhh@11 {
        compatible = "st,lis3dhh","st,spi_lis3dhh";
        reg = <0x11>;
        label = "LIS3DHH";
        spi-max-frequency = <10000000>; /*max. 10MHz*/
        int1-gpios = <&gpioc 7 GPIO_ACTIVE_HIGH>; /*PC7*/
        int2-gpios = <&gpioc 8 GPIO_ACTIVE_HIGH>;  /*PC8 */
    };
};

Any suggestions, hints or directions are very welcome.
Thanks in advance,
Markus