Hi, In order to handle the PCIe specific usage, used to describe the PCI I/O and memory regions (as described in IEEE Std 1275-1994), the standard ranges property is used and must be parsed and

Reminder: Zephyr Project: Dev Meeting When: 10/14/2021 3:00pm to 4:00pm (UTC+00:00) UTC Where: Microsoft Teams Meeting Organizer: devel@... An RSVP is requested. Click here to

drivers: syscon: Set default for CONFIG_SYSCON to y - https://github.com/zephyrproject-rtos/zephyr/pull/38762 Plus anything anyone else has. - k

Hello everyone, We recently made changes to the project roles and the access levels given to contributors on github. Please refer to the full documentation of the roles below for more

Hi. I’ve created a request for comments to split the zephyr project maintained repository trusted-firmware-m into a fork of the individual upstream repositories More details in the RFC github issue:

Hi There, Thanks to everyone for the feedback thus far, it is really appreciated. Our plan is to modify the code that affects the arch/riscv for smp support so that it is generic/agnostic. We will

Hi Zephyr Community! We are very happy to announce the 5th (and likely last) release candidate for the v2.7.0 LTS \o/ https://github.com/zephyrproject-rtos/zephyr/releases/tag/v2.7.0-rc5 This

Reminder: Zephyr Project: APIs When: 10/12/2021 4:00pm to 5:00pm (UTC+00:00) UTC Where: Microsoft Teams Meeting Organizer: devel@... An RSVP is requested. Click here to

Hi all, I won't be able to attend today's meeting, but Keith has kindly offered his help chairing it. Agenda for today: - PM structure optimization - Issue:

Hi Zhihao, Thank you for your contribution. Please submit it as a pull request on GitHub. See https://docs.zephyrproject.org/latest/contribute/index.html#contribution-workflow for detailed

There is no built-in SDRAM area in mimxrt1061 cvl5a, which makes zephyr unable to work on 1061 SOC Best Regards Zhihao

I believe qemu also has models for the SMP SiFive models (which, I'd expect, have a very similar CPU complex to the PolarFire). Making sure that the port works there to enable a broader set of

Reminder: Zephyr Project: Dev Meeting When: 10/07/2021 3:00pm to 4:00pm (UTC+00:00) UTC Where: Microsoft Teams Meeting Organizer: devel@... An RSVP is requested. Click here to

I am not sure if it is suitable for dev-review, otherwise for the next API meeting: - Improve API headers documentation https://github.com/zephyrproject-rtos/zephyr/issues/30466

Will bring this up and see if discussion in API meeting is more appropriate: - Improve API headers documentation https://github.com/zephyrproject-rtos/zephyr/issues/30466 - k

Just for clarity, this is the agenda for October 7, NOT October 6. Meeting starts in about half an hour as usual.

Conor, Thank you for sharing, this is great. Just a quick comment, from a quick look at the links below, I noticed the arch changes to riscv adding smp support and other generic code references your

Hi, There is no information about tinycrypt being EOL on webpage nor github... https://github.com/intel/tinycrypt https://01.org/tinycrypt -- pozdrawiam Szymon K. Janc

Hi Conor We have tried to run it in Renode and everything worked as expected! We checked the smp/pi sample and some other basic apps like hello-world or synchronization. We'd be happy to review it

Hi there, We have been working on a port of zephyr for the Microchip PolarFire SoC Icicle Kit, focusing on SMP support. It is very much in initial stages, however, we have tested it on our hardware