Hi David,

It is still possible to assert bit-field implementation (static assert). Then in case of incompatibilities we will have an early porting alarm. This could be done even once for a SoC. Andrzej

Boie, Andrew P wrote: Yeah, this is sorta wrong. GCC[1] is AFAIK consistent and sane within a single architecture, but the packing order varies between endianness conventions and officially they

I think we have a fair number of drivers that define structs that use the above technique, to have fields in the struct which correspond to particular bits in a register. Or see the data structures

One other protocol I just realized is already out there is lwm2m. There is starting to be some support for it in Zephyr, it works over other transports, supports device management, and has support

I believe the answer is that the transition to using the DTS will occur when the structure generation support is solidified. If you look at the outdir/<STM board>/include/generated/ directory you will

surfing in the sources tree I can find dts/arm/st/stm32f412-pinctrl.dtsi usart3_pins_a: usart3@0 { rx_tx { rx = <STM32_PIN_PB11 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)>; tx =

Hi David, Thanks for the feedback.

My first suggestion. Unless we are stricly implementing the USB DFU protocol, we really should call this something else. DFU is defined by USB standards, and is a very specific protocol with a very

Hi Johann, Thanks for the feedback.

Hi, That surprised me a little, can you describe it in more detail what you mean with "it maps specifically to particular USB endpoints and classes". I think if you have USB, then USB DFU is the most

Hi all, As you might already know, we've been working on the introduction of DFU (Device Firmware Upgrade) to Zephyr. Several Pull Requests have been posted dealing with the low-level flash and image

Hi Martï, Sorry for the huge delay on this, it slipped through the cracks! Regarding Meson, I actually don’t think this is a bad idea at all, the list you mention: - is cross-platform

Hi Jukka, I believe you are talking about a solution used currently by Zephyr's I2C API. There we have: union dev_config { u32_t raw; struct __bits { u32_t use_10_bit_addr :

Hi Erwin, I have no prererence here, using the bit field values is usually quite convenient but it really depends how you are using these values. You could have both ways if you put a union inside

In the counter API we can find following function with its description: /** * @brief Set an alarm. * @param dev Pointer to the device structure for the driver instance. * @param callback Pointer to

Hello, maybe a bit of a weird coding style question, but for CAN support I need a CAN ID "struct". The CAN ID is a 11 or 29 bit ID, a flags that says it is 29 or 11 bit, a RTR flag and possible a

Hi Maciej, As I understand it (I may be wrong), the code above does not handle the case of stm32f0 where the main Flash memory is aliased in the boot memory space (0x0000 0000), but still accessible

Hello developers, As current watchdog API looks like legacy from QMSI I would like to propose some refresh. My RFC adds support for watchdogs with multiple reload channels. It also enables

Gentlemen, thank you for your quick responses! As I wanted to provide more info and debug output, I accidentally found the issue. This little change in arch/arm/core/cortex_m/prep_c.c caused sys fatal