On 23 Aug 2019, at 16:32, Manu R <manu@...> wrote:

Thanks Anas, I should have been clearer in my question, apologies.

It looks like there is a 1.14.1 brewing, I presume that is bug fixes on the 1.14 release. When it is released, I will probably want that, but for now, the last released version is v1.14.0, is that correct?

Manu

On Fri, Aug 23, 2019 at 4:24 PM Nashif, Anas <anas.nashif@...> wrote:
v1.14-branch is the branch, all others are tags on the branch.



Anas





From: <devel@...> on behalf of Manu R <manu@...>
Date: Friday, 23 August 2019 at 18:38
To: "devel@..." <devel@...>
Subject: [Zephyr-devel] What branch should I be using for the 1.14 LTS release?



when I do a zephyr (v1.14-branch) $ git checkout v1.14<tab>
v1.14-branch v1.14.0 v1.14.0-rc1 v1.14.0-rc2 v1.14.0-rc3 v1.14.1-rc1



Thanks

Manu

------------------------------------------------------------------

发件人：Andy Ross <andrew.j.ross@...>

发送时间：2019年8月23日(星期五) 23:35

收件人：曹子龙 <caozilong@...>; devel <devel@...>

主　题：Re: [Zephyr-devel] Is The tick handler "z_clock_announce" in SMP mode dupulicate caculated？

This is the responsibility of the timer driver.  The ticks announced needs to be globally correct.  The existing drivers do this by locking a "last count" state variable and updating it, so they see the updates made by the other cores.

Andy

On 8/23/2019 8:14 AM, "曹子龙 wrote:

Hi  friends:

    

  a puzzle in the timer tick interrupt handler in SMP mode.  look at below,  the SMP mult cores share the same "cur_tick" object to remeber the current time, each cpu would increment it when the tick hander  excutes on each CPU.

so, could this would accelerate the timer compare with the realworld?  for example, if 4cores  exist, the cur_tick would 4 times incmrent than the read world, i cant fingure out where am a wrong, so, could you figure me out?  thanks for your kinldy supply. 

void z_clock_announce(s32_t ticks)

{

#ifdef CONFIG_TIMESLICING

 z_time_slice(ticks);

#endif

 k_spinlock_key_t key = k_spin_lock(&timeout_lock);

 announce_remaining = ticks;

 while (first() != NULL && first()->dticks <= announce_remaining) {

  struct _timeout *t = first();

  int dt = t->dticks;

  curr_tick += dt;

  announce_remaining -= dt;

  t->dticks = 0;

  remove_timeout(t);

  k_spin_unlock(&timeout_lock, key);

  t->fn(t);

  key = k_spin_lock(&timeout_lock);

 }

 if (first() != NULL) {

  first()->dticks -= announce_remaining;

 }

 curr_tick += announce_remaining;

 announce_remaining = 0;

 z_clock_set_timeout(next_timeout(), false);

 k_spin_unlock(&timeout_lock, key);

}

曹子龙

珠海全志科技股份有限公司      BU1-PSW

地址：广东省珠海市高新区唐家湾镇科技2路9号

TEL：13824125580

Email：caozilong@...

网址： http://www.allwinnertech.com

 

------------------------------------------------------------------
发件人：Andy Ross<andrew.j.ross@...>
日　期：2019年08月23日 23:32:07
收件人：曹子龙<caozilong@...>; devel<devel@...>
主　题：Re: [Zephyr-devel] Is The tick handler "z_clock_announce" in SMP mode dupulicate caculated？

This is the responsibility of the timer driver.  The ticks announced needs to be globally correct.  The existing drivers do this by locking a "last count" state variable and updating it, so they see the updates made by the other cores.

Andy

On 8/23/2019 8:14 AM, "曹子龙 wrote:

Hi  friends:

    

  a puzzle in the timer tick interrupt handler in SMP mode.  look at below,  the SMP mult cores share the same "cur_tick" object to remeber the current time, each cpu would increment it when the tick hander  excutes on each CPU.

so, could this would accelerate the timer compare with the realworld?  for example, if 4cores  exist, the cur_tick would 4 times incmrent than the read world, i cant fingure out where am a wrong, so, could you figure me out?  thanks for your kinldy supply. 

void z_clock_announce(s32_t ticks)

{

#ifdef CONFIG_TIMESLICING

 z_time_slice(ticks);

#endif

 k_spinlock_key_t key = k_spin_lock(&timeout_lock);

 announce_remaining = ticks;

 while (first() != NULL && first()->dticks <= announce_remaining) {

  struct _timeout *t = first();

  int dt = t->dticks;

  curr_tick += dt;

  announce_remaining -= dt;

  t->dticks = 0;

  remove_timeout(t);

  k_spin_unlock(&timeout_lock, key);

  t->fn(t);

  key = k_spin_lock(&timeout_lock);

 }

 if (first() != NULL) {

  first()->dticks -= announce_remaining;

 }

 curr_tick += announce_remaining;

 announce_remaining = 0;

 z_clock_set_timeout(next_timeout(), false);

 k_spin_unlock(&timeout_lock, key);

}

曹子龙

珠海全志科技股份有限公司      BU1-PSW

地址：广东省珠海市高新区唐家湾镇科技2路9号

TEL：13824125580

Email：caozilong@...

网址： http://www.allwinnertech.com

 

Hi  friends:

    

  a puzzle in the timer tick interrupt handler in SMP mode.  look at below,  the SMP mult cores share the same "cur_tick" object to remeber the current time, each cpu would increment it when the tick hander  excutes on each CPU.

so, could this would accelerate the timer compare with the realworld?  for example, if 4cores  exist, the cur_tick would 4 times incmrent than the read world, i cant fingure out where am a wrong, so, could you figure me out?  thanks for your kinldy supply. 

void z_clock_announce(s32_t ticks)

{

#ifdef CONFIG_TIMESLICING

 z_time_slice(ticks);

#endif

 k_spinlock_key_t key = k_spin_lock(&timeout_lock);

 announce_remaining = ticks;

 while (first() != NULL && first()->dticks <= announce_remaining) {

  struct _timeout *t = first();

  int dt = t->dticks;

  curr_tick += dt;

  announce_remaining -= dt;

  t->dticks = 0;

  remove_timeout(t);

  k_spin_unlock(&timeout_lock, key);

  t->fn(t);

  key = k_spin_lock(&timeout_lock);

 }

 if (first() != NULL) {

  first()->dticks -= announce_remaining;

 }

 curr_tick += announce_remaining;

 announce_remaining = 0;

 z_clock_set_timeout(next_timeout(), false);

 k_spin_unlock(&timeout_lock, key);

}

曹子龙

珠海全志科技股份有限公司      BU1-PSW

地址：广东省珠海市高新区唐家湾镇科技2路9号

TEL：13824125580

Email：caozilong@...

网址： http://www.allwinnertech.com

 

Can I use west to initialize multiple working directories?

 

I’m experimenting with adding a module and I wanted to a setup so I created a ‘zephyrproject_2’ directory and ran a ‘west init’ command with some additional parameters to use the west.yaml of my url/branch but it returns an error which leads me to think a system can only have one installation:

 

FATAL ERROR: already in an installation (/home/dleach/work/zephyrproject), aborting

 

David Leach

 

NXP Semiconductors

phone: +1.210.241.6761

Email: david.leach@...

 

 

** PROPRIETARY & COMPANY-CONFIDENTIAL **

 

Can I use west to initialize multiple working directories?

 

I’m experimenting with adding a module and I wanted to a setup so I created a ‘zephyrproject_2’ directory and ran a ‘west init’ command with some additional parameters to use the west.yaml of my url/branch but it returns an error which leads me to think a system can only have one installation:

 

FATAL ERROR: already in an installation (/home/dleach/work/zephyrproject), aborting

 

David Leach

 

NXP Semiconductors

phone: +1.210.241.6761

Email: david.leach@...

 

 

** PROPRIETARY & COMPANY-CONFIDENTIAL **

 

Can I use west to initialize multiple working directories?

 

I’m experimenting with adding a module and I wanted to a setup so I created a ‘zephyrproject_2’ directory and ran a ‘west init’ command with some additional parameters to use the west.yaml of my url/branch but it returns an error which leads me to think a system can only have one installation:

 

FATAL ERROR: already in an installation (/home/dleach/work/zephyrproject), aborting

 

David Leach

 

NXP Semiconductors

phone: +1.210.241.6761

Email: david.leach@...

 

 

** PROPRIETARY & COMPANY-CONFIDENTIAL **

 

Can I use west to initialize multiple working directories?

 

I’m experimenting with adding a module and I wanted to a setup so I created a ‘zephyrproject_2’ directory and ran a ‘west init’ command with some additional parameters to use the west.yaml of my url/branch but it returns an error which leads me to think a system can only have one installation:

 

FATAL ERROR: already in an installation (/home/dleach/work/zephyrproject), aborting

 

David Leach

 

NXP Semiconductors

phone: +1.210.241.6761

Email: david.leach@...

 

 

** PROPRIETARY & COMPANY-CONFIDENTIAL **