Hello, Hmm... It seems that in CONFIG_USE_SWITCH=n case (ex. aarch32(*)) _current_cpu.current is updated by software interrupt handler. (*) arch/arm/core/aarch32/swap_helper.S So I wonder that why CON

Hello, I can check it directly. I think this is future work to achieve more faster switching than now. At this point, I want to implement most conservative one.. Best Regards, Katsuhiro Suzuki

Hello, Thanks for your advice. Current RISC-V implementation (CONFIG_USE_SWITCH=n) is using 'ecall' (this is SW interrupt instruction) to execute context switching explicitly. And jump into interrupt

Hello, Thank you for reply. Currently, No. I'm trying to add a support for CONFIG_USE_SWITCH=y case. Sorry for confusing. Older means CONFIG_USE_SWITCH=n. Does not means Zephyr's version. Because to k

Hello kernel guys, I have question about newer version of context switching (CONFIG_USE_SWITCH=y). Newer switching sets NEW thread handle into _current_cpu.current BEFORE calling arch_switch(). This i

Hello Maureen-san, I have one question. Who is most suitable person if we want to discuss or merge RISC-V subsystem and RISC-V related drivers (not core kernel)? It seems that mainly Nashif and Gala d

Hello Carles, Indeed, thanks for your positive opinion. I'll continue to try to check (and also study :) ) existing issues or PRs. Best Regards, Katsuhiro Suzuki

Hello Carles, Thank you for reply. I understand situation. I will try to add myself as collaborator of watchdog. But it seems that Zephyr project rules need two or more reviewers to proceed pull reque

Hello, It seems that watchdog driver is orphaned. I would be appreciate it if anyone inform about that... Best Regards, Katsuhiro Suzuki

Hello All, I'm implementing Watchdog driver for HiFive1 Rev.b. This watchdog can reset SoC immediately when counter is reaching timeout. It's suitable feature of WDT_FLAG_RESET_SOC. But tests/drivers/

Hello, Thanks for great works! I'm trying: zephyr-toolchain-riscv64-0.12.0-beta-2-x86_64-linux-setup.run Currently, it works fine for me. Best Regards, Katsuhiro Suzuki

Hello Maureen-san, Sorry for late, I created PR 30033 that just adds myself to collaborators. https://github.com/zephyrproject-rtos/zephyr/pull/30033 Best Regards, Katsuhiro Suzuki

Hello Maureen, I want to join as collaborators. Would you tell me how to add? By pull request? Best Regards, Katsuhiro Suzuki

Hello Andrew, Thanks for comments. I understand you are fixing the problem. Currently we cannot trust sanitycheck results for SMP. And in last month, you told me there are no active maintainer in RISC

Hello, I'm continuing to try and fix bugs of SMP support for RISC-V. My first target is my patches pass the 'sanitycheck' and 'buildkite' tests. I'm facing strange behavior of sanitycheck currently: -

Hi Andrew, Oh... I didn't check MAINTAINERS.yaml. Hmm... Can I help this issue? Are you talking about this PR? https://github.com/zephyrproject-rtos/zephyr/pull/27063 I have HiFive Unleashed (RV64 boa

Hello, Who is maintainer of RISC-V porting area? I want to discuss about SMP support for RISC-V with maintainer(s). Near a week ago, I posted SMP support for RISC-V and few days ago Jim Shu from Andes

Hello Andrew, Kumar, Thank you for pointing about regression tests. Yes, right. For sanitycheck, I added another patch to change configs of qemu_rv32_virt board. It selected CONFIG_USE_SWITCH and rela

Hello Kumar, Sorry for multi posting. Zephyr ML has very long delay to deliver my mail...?? Anyway, thanks a lot for your comment. I'll add the config. BTW, QEMU can choose SMP mode or non-SMP mode by

Hello All, I'm working on SMP support for RISC-V privilege architecture. https://github.com/katsuster/zephyr/tree/riscv_virt_pc_smp It seems worked well on QEMU RV32 virt pc (*) porting. (RV64 not tes