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RISC-V maintainers and collaborators
Hello Maureen-san, I have one question. Who is most suitable person if we want to discuss or merge RISC-V subsystem and RISC-V related drivers (not core kernel)? It seems that mainly Nashif and Gala d
Hello Maureen-san, I have one question. Who is most suitable person if we want to discuss or merge RISC-V subsystem and RISC-V related drivers (not core kernel)? It seems that mainly Nashif and Gala d
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By
Katsuhiro Suzuki
· #7519
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What is expected behavior of watchdog with WDT_FLAG_RESET_SOC?
Hello Carles, Indeed, thanks for your positive opinion. I'll continue to try to check (and also study :) ) existing issues or PRs. Best Regards, Katsuhiro Suzuki
Hello Carles, Indeed, thanks for your positive opinion. I'll continue to try to check (and also study :) ) existing issues or PRs. Best Regards, Katsuhiro Suzuki
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By
Katsuhiro Suzuki
· #7485
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What is expected behavior of watchdog with WDT_FLAG_RESET_SOC?
Hello Carles, Thank you for reply. I understand situation. I will try to add myself as collaborator of watchdog. But it seems that Zephyr project rules need two or more reviewers to proceed pull reque
Hello Carles, Thank you for reply. I understand situation. I will try to add myself as collaborator of watchdog. But it seems that Zephyr project rules need two or more reviewers to proceed pull reque
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By
Katsuhiro Suzuki
· #7483
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What is expected behavior of watchdog with WDT_FLAG_RESET_SOC?
Hello, It seems that watchdog driver is orphaned. I would be appreciate it if anyone inform about that... Best Regards, Katsuhiro Suzuki
Hello, It seems that watchdog driver is orphaned. I would be appreciate it if anyone inform about that... Best Regards, Katsuhiro Suzuki
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By
Katsuhiro Suzuki
· #7477
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What is expected behavior of watchdog with WDT_FLAG_RESET_SOC?
Hello All, I'm implementing Watchdog driver for HiFive1 Rev.b. This watchdog can reset SoC immediately when counter is reaching timeout. It's suitable feature of WDT_FLAG_RESET_SOC. But tests/drivers/
Hello All, I'm implementing Watchdog driver for HiFive1 Rev.b. This watchdog can reset SoC immediately when counter is reaching timeout. It's suitable feature of WDT_FLAG_RESET_SOC. But tests/drivers/
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By
Katsuhiro Suzuki
· #7470
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Zephyr SDK 0.12.0-beta-2 available for testing
Hello, Thanks for great works! I'm trying: zephyr-toolchain-riscv64-0.12.0-beta-2-x86_64-linux-setup.run Currently, it works fine for me. Best Regards, Katsuhiro Suzuki
Hello, Thanks for great works! I'm trying: zephyr-toolchain-riscv64-0.12.0-beta-2-x86_64-linux-setup.run Currently, it works fine for me. Best Regards, Katsuhiro Suzuki
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By
Katsuhiro Suzuki
· #7466
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RISC-V maintainers and collaborators
Hello Maureen-san, Sorry for late, I created PR 30033 that just adds myself to collaborators. https://github.com/zephyrproject-rtos/zephyr/pull/30033 Best Regards, Katsuhiro Suzuki
Hello Maureen-san, Sorry for late, I created PR 30033 that just adds myself to collaborators. https://github.com/zephyrproject-rtos/zephyr/pull/30033 Best Regards, Katsuhiro Suzuki
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By
Katsuhiro Suzuki
· #7457
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RISC-V maintainers and collaborators
Hello Maureen, I want to join as collaborators. Would you tell me how to add? By pull request? Best Regards, Katsuhiro Suzuki
Hello Maureen, I want to join as collaborators. Would you tell me how to add? By pull request? Best Regards, Katsuhiro Suzuki
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By
Katsuhiro Suzuki
· #7452
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Question about the sanitycheck for SMP
Hello Andrew, Thanks for comments. I understand you are fixing the problem. Currently we cannot trust sanitycheck results for SMP. And in last month, you told me there are no active maintainer in RISC
Hello Andrew, Thanks for comments. I understand you are fixing the problem. Currently we cannot trust sanitycheck results for SMP. And in last month, you told me there are no active maintainer in RISC
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By
Katsuhiro Suzuki
· #7446
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Question about the sanitycheck for SMP
Hello, I'm continuing to try and fix bugs of SMP support for RISC-V. My first target is my patches pass the 'sanitycheck' and 'buildkite' tests. I'm facing strange behavior of sanitycheck currently: -
Hello, I'm continuing to try and fix bugs of SMP support for RISC-V. My first target is my patches pass the 'sanitycheck' and 'buildkite' tests. I'm facing strange behavior of sanitycheck currently: -
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By
Katsuhiro Suzuki
· #7444
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SMP support for RISC-V privilege architecture
Hi Andrew, Oh... I didn't check MAINTAINERS.yaml. Hmm... Can I help this issue? Are you talking about this PR? https://github.com/zephyrproject-rtos/zephyr/pull/27063 I have HiFive Unleashed (RV64 boa
Hi Andrew, Oh... I didn't check MAINTAINERS.yaml. Hmm... Can I help this issue? Are you talking about this PR? https://github.com/zephyrproject-rtos/zephyr/pull/27063 I have HiFive Unleashed (RV64 boa
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By
Katsuhiro Suzuki
· #7392
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SMP support for RISC-V privilege architecture
Hello, Who is maintainer of RISC-V porting area? I want to discuss about SMP support for RISC-V with maintainer(s). Near a week ago, I posted SMP support for RISC-V and few days ago Jim Shu from Andes
Hello, Who is maintainer of RISC-V porting area? I want to discuss about SMP support for RISC-V with maintainer(s). Near a week ago, I posted SMP support for RISC-V and few days ago Jim Shu from Andes
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By
Katsuhiro Suzuki
· #7390
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[RFC] SMP support for RISC-V privilege architecture
Hello Andrew, Kumar, Thank you for pointing about regression tests. Yes, right. For sanitycheck, I added another patch to change configs of qemu_rv32_virt board. It selected CONFIG_USE_SWITCH and rela
Hello Andrew, Kumar, Thank you for pointing about regression tests. Yes, right. For sanitycheck, I added another patch to change configs of qemu_rv32_virt board. It selected CONFIG_USE_SWITCH and rela
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By
Katsuhiro Suzuki
· #7380
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[RFC] SMP support for RISC-V privilege architecture
Hello Kumar, Sorry for multi posting. Zephyr ML has very long delay to deliver my mail...?? Anyway, thanks a lot for your comment. I'll add the config. BTW, QEMU can choose SMP mode or non-SMP mode by
Hello Kumar, Sorry for multi posting. Zephyr ML has very long delay to deliver my mail...?? Anyway, thanks a lot for your comment. I'll add the config. BTW, QEMU can choose SMP mode or non-SMP mode by
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By
Katsuhiro Suzuki
· #7372
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[RFC] SMP support for RISC-V privilege architecture
Hello All, I'm working on SMP support for RISC-V privilege architecture. https://github.com/katsuster/zephyr/tree/riscv_virt_pc_smp It seems worked well on QEMU RV32 virt pc (*) porting. (RV64 not tes
Hello All, I'm working on SMP support for RISC-V privilege architecture. https://github.com/katsuster/zephyr/tree/riscv_virt_pc_smp It seems worked well on QEMU RV32 virt pc (*) porting. (RV64 not tes
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By
Katsuhiro Suzuki
· #7367
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[RFC] SMP support for RISC-V privilege architecture
Hello All, I'm working on SMP support for RISC-V privilege architecture. https://github.com/katsuster/zephyr/tree/riscv_virt_pc_smp It seems worked well on QEMU RV32 virt pc (*) porting. (RV64 not tes
Hello All, I'm working on SMP support for RISC-V privilege architecture. https://github.com/katsuster/zephyr/tree/riscv_virt_pc_smp It seems worked well on QEMU RV32 virt pc (*) porting. (RV64 not tes
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By
Katsuhiro Suzuki
· #7366
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[RFC] SMP support for RISC-V privilege architecture
Hello All, I'm working on SMP support for RISC-V privilege architecture. https://github.com/katsuster/zephyr/tree/riscv_virt_pc_smp It seems worked well on QEMU RV32 virt pc (*) porting. (RV64 not tes
Hello All, I'm working on SMP support for RISC-V privilege architecture. https://github.com/katsuster/zephyr/tree/riscv_virt_pc_smp It seems worked well on QEMU RV32 virt pc (*) porting. (RV64 not tes
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By
Katsuhiro Suzuki
· #7365
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