Hi,

i have reviewed the cortex-m arch about the interrupt flow, and
found that cortex-m support max 255 interrupt entry and it
allows interrupt with higher prio preempted another one with
lower priority interrupt,

i did not see other arch`s code but just want to know about, is this
the feature of zephyr kernel? for the strong real-time feature? or
arch related?

Should be supported on architectures where the hardware has support for
it. It is a feature of the kernel.

ARM, ARC, x86 do support it.

Not entirely sure about Nios2 and RiscV.

Regards,
Ben

--
Benjamin Walsh, SMTS
WR VxWorks Virtualization Profile
www.windriver.com
Zephyr kernel maintainer
www.zephyrproject.org

Should be supported on architectures where the hardware has support for it. It is a feature of the kernel.

ARM, ARC, x86 do support it.

[ChuckJ] To clarify. On ARC, FIRQ can be nested on top of RIRQ. But at this time RIRQ cannot be nested on top of RIRQ.
Some assembly language has to be re-organized in Zephyr to allow for this.
But yes, as a goal, nested interrupts are desired.

i did not see other arch`s code but just want to know about, is this
the feature of zephyr kernel? for the strong real-time feature? or
arch related?

Should be supported on architectures where the hardware has support for it.
It is a feature of the kernel.

ARM, ARC, x86 do support it.

Not entirely sure about Nios2 and RiscV.

On Nios II we currently just support the very simple IIC (Internal Interrupt Controller) and nested interrupts aren't possible.

Andrew