Xtensa architecture support in LLVM

Ivan Grokhotkov <ivan@...>


Since Zephyr RTOS includes support for the Xtensa architecture, I'd like to bring attention to the Xtensa LLVM backend, which is currently in review on LLVM Phabircator. This backend was developed by Espressif, with the initial targets being ESP8266 and ESP32 chips.
As some of the Zephyr developers (mainly from Intel) have access to the Xtensa architecture documentation, we would like to ask for reviews on this series of patches.
I think having Xtensa supported in LLVM would also be beneficial for the Zephyr project, as the LLVM backend allows adding new Xtensa core configurations in a much more straightforward way, compared to GCC.

Links to the patch series:

D64826: [Xtensa 1/10] Recognize Xtensa in triple parsing code.
D64827: [Xtensa 2/10] Add Xtensa ELF definitions.
D64829: [Xtensa 3/10] Add initial version of the Xtensa backend.
D64830: [Xtensa 4/10] Add basic *td files with Xtensa architecture description.
D64831: [Xtensa 5/10] Add Xtensa MCTargetDescr initial functionality.
D64832: [Xtensa 6/10] Add Xtensa basic assembler parser.
D64833: [Xtensa 7/10] Add Xtensa instruction printer.
D64834: [Xtensa 8/10] Add support of the Xtensa shift/load/store/move and processor control instructions.
D64835: [Xtensa 9/10] Add basic support of Xtensa disassembler.
D64836: [Xtensa 10/10] Add relaxations and fixups. Add rest part of Xtensa Core Instructions.

The patches are maintained at This repository can also be used to submit issues.

Thank you,
Ivan Grokhotkov
Espressif Systems