Hi all, While I was working on the errno transition patchset, I realized all driver APIs (i2c, spi, gpio, etc.) return 'int' type, but pinmux APIs. For the sake of consistency, I think we should chang

I downloaded the Zephyr SDK v0.7.2 last night and tried to install it this morning on my MacBook. During the installation, I cancelled with ctrl-C and somehow it seems to have executed a "rm -rf /" (a

Hi, I would like to propose some changes to the public GPIO API. Addressing major 2 issues which I faced while writing some code using the API. And an third one, related to the consistency of the API.

Hi, I'm looking to use the spi interface on the FRDM-K64f board, is there a driver for that? Or alternatively, is it all right for for me to change and mess with the clock settings for the board? Will

Hi everyone, is it just me or everyone does not receive some emails to their inbox from the devel mailing list? For example I did not receive any email for the threads: [RFC] GPIO API changes FRDM-K64

Hi, I am experiencing problems with access to Zephyr sites. I can no longer login into Zephyr gerrit :-( I have checked my linuxfoundation.org login and it only works from Firefox, I can not login fro

Hi all, I've published version 10 of the patchset adding STM32/STM32F1 support. I will update the series once Anas merges his arch/arm/soc tree layout changes. The code is also available here in branc

From: Simon Desfarges <simon.desfarges(a)intel.com> ASSERT are put each time the timer0 limit register or the timer0 count register is modified. Change-Id: I38684d57803de285f4e26c68b449c71396e4c750 Tr

From: Simon Desfarges <simon.desfarges(a)intel.com> Hello, I am trying to enable the tickless idle of ARC in our project. Here is my problem. OS: Zephyr 1.0.0 Processor: Quark_se The ARC TICK timer co

From: Simon Desfarges <simon.desfarges(a)intel.com> When exiting from tickless idle uppon an external IRQ, the TICK timer is set to fire at next TICK boundary. The current algorithm can lead to a poin

Hi, I have posted version 13 of the patchset. As usual the series is avaialable in my github repo https://github.com/bboozzoo/zephyr/ in branch bboozzoo/stm32f10x-for-upstream-v13. Changelog =========

[Revised incorporating feedbacks so far] Problem Statement: Power management Kconfig flags are not consistent and hierarchy is not clear Why this is a problem: ----------------------------- The names

[Revised incorporating feedbacks. The changes are shown at the end] Problem Statement: Not all Zephyr kernel drivers provide the same interfaces. Why this is a problem: ----------------------------- T

(Revised and incorporated feedbacks. The term "Tickless Idle" was found confusing to be used to refer to a PM policy. That is a specific term used for an optimized kernel idling mechanism saving power

Hi, I have a Freescale FRDM-K64 board. I cannot get the samples/hello_world/microkernel to work. Compiling with this: # make O=out-arm BOARD=frdm_k64f It compiles fine and the out-arm/zephyr.bin can b

Hi, I am trying to use GPIO on my Freescale FRDM-K64 board. However, I cannot seem to find the driver name. It from this page that the driver name should be something like CONFIG_GPIO_<VENDOR_<MCU>_PO

From: Simon Desfarges <simon.desfarges(a)intel.com> The timer counts from 0 to programmed_limit included. Change-Id: Ifc8585210c319f5452fafc911d4f6d72c4b91eaa Tracked-On: https://jira.ndg.intel.com/br

From: Simon Desfarges <simon.desfarges(a)intel.com> When exiting from tickless idle uppon an external IRQ, the TICK timer is set to fire at next TICK boundary. The current algorithm can lead to a poin

From: Simon Desfarges <simon.desfarges(a)intel.com> ASSERT are put each time the timer0 limit register or the timer0 count register is modified. Change-Id: I38684d57803de285f4e26c68b449c71396e4c750 Tr

[Rev 1.2 - Added a parameter to .suspend() and .resume() functions indicating the power policy used by the PMA. This parameter will help driver take policy based optimized actions. Described in detail