Running Zephyr on Arty, #litex


Hi, I've been trying to get a Zephyr sample running on the Arty FPGA-board without succeeding.
I’ve tried both using the zephyr-sdk toolchain and cross-compile toolchain with the same unsatisfying result.
Litex boots fine and firmware is uploaded but then nothing.

Is there any working prebuilt Litex gateware – Zephyr firmware combination available to test with?


printenv | grep ZEPHYR
stefan@virtLinux:~/FPGA/Zeph/zephyr$ ls
arch    CMakeLists.txt      doc      include         lib       modules     soc
boards  drivers  Kconfig         LICENSE   README.rst  subsys   west.yml
build   CODEOWNERS          dts      Kconfig.zephyr  Makefile  samples     tests    zephyr-env.cmd
cmake   CONTRIBUTING.rst    ext      kernel          misc      scripts     VERSION
stefan@virtLinux:~/FPGA/Zeph/zephyr$ west build -b litex_vexriscv samples/hello_world
-- west build: build configuration:
       source directory: /home/stefan/FPGA/Zeph/zephyr/samples/hello_world
       build directory: /home/stefan/FPGA/Zeph/zephyr/build
       BOARD: litex_vexriscv (origin: CMakeCache.txt)
-- west build: building application
ninja: no work to do.
stefan@virtLinux:~/FPGA/Zeph/zephyr$ lxterm --serial-boot --kernel build/zephyr/zephyr.bin /dev/ttyUSB1
[LXTERM] Starting....

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <

 (c) Copyright 2012-2019 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs Ltd

 BIOS built on Aug 27 2019 22:09:58
 BIOS CRC passed (354dfde9)

 Migen git sha1: --------
 LiteX git sha1: 5a7b4c34

--============ SoC info ================--
CPU:       VexRiscv @ 100MHz
ROM:       32KB
SRAM:      32KB
L2:        8KB
MAIN-RAM:  262144KB

--========= Peripherals init ===========--
Initializing SDRAM...
SDRAM now under software control
Read leveling:
m0, b0: |11111100000000000000000000000000| delays: 03+-03
m0, b1: |00000000000011111111100000000000| delays: 16+-04
m0, b2: |00000000000000000000000000001111| delays: 30+-02
m0, b3: |00000000000000000000000000000000| delays: -
m0, b4: |00000000000000000000000000000000| delays: -
m0, b5: |00000000000000000000000000000000| delays: -
m0, b6: |00000000000000000000000000000000| delays: -
m0, b7: |00000000000000000000000000000000| delays: -
best: m0, b1 delays: 16+-04
m1, b0: |11111111100000000000000000000000| delays: 04+-04
m1, b1: |00000000000001111111111100000000| delays: 18+-05
m1, b2: |00000000000000000000000000000111| delays: 30+-01
m1, b3: |00000000000000000000000000000000| delays: -
m1, b4: |00000000000000000000000000000000| delays: -
m1, b5: |00000000000000000000000000000000| delays: -
m1, b6: |00000000000000000000000000000000| delays: -
m1, b7: |00000000000000000000000000000000| delays: -
best: m1, b1 delays: 18+-05
SDRAM now under hardware control
Memtest OK

--========== Boot sequence =============--
Booting from serial...
Press Q or ESC to abort boot completely.
[LXTERM] Received firmware download request from the device.
[LXTERM] Uploading build/zephyr/zephyr.bin to 0x40000000 (9608 bytes)...
[LXTERM] Upload complete (7.7KB/s).
[LXTERM] Booting the device.
[LXTERM] Done.
Executing booted program at 0x40000000
--============= Liftoff! ===============--

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