From what I checked:
- A. 74 clocks stop with a change in CS without sufficient delay
- B. CMD0 (0x40 0x00 0x00 0x00 0x00 0x94) fails to send 0x40... (instead send 0x20...)
- C. CMD0 fails to receive 0x01
I added `k_usleep(30); // usec` before sdhc_spi_set_cs(data, 0); in sdhc_spi_go_idle() of disk_access_spi_sdhc.c.
Then, the above A and B are solved.
However, I still have the problem of C.
This may be caused without sufficient delay after sending 0x94. I am checking how to add delay after 0x94.
I also checked the clock frequency.
- STM32L476: 312kHz
- STM32F768: 210kHz
I am not sure whether this difference in the frequency makes the failure and success of the process.