Re: SMT32F103 - RCC_CFGR_PLLXTPRE not set correctly?

Erwan Gouriou

Hi Naro,

Have you tried to revert the faulty commit and see if this fixes the issue in your case ?
(To make it work, you might have to remove #ifdefery around `SOC_STM32F10X_DENSITY_DEVICE`.


On Thu, 11 Feb 2021 at 18:25, immanuel narodoslawsky <narodo.imm@...> wrote:
Hi everyone,

I have troubles getting my custom board to work. I think the problem is that the RCC_CFGR_PLLXTPRE bit is not handled properly. I am using an STM32F103C8 (same as on the bluebill board) with an external 16MHz quartz. I am trying to run the system on 72MHz by dividing the input clock by 2.
Currently I am on Zephyr 2.4.0, but as far as I can see this is still the same for the latest version.

I saw that this config option was removed in commit 6b72fbae7c  since the HAL layer is supposed to handle this, but I can't quite see how.

If I follow the calls I end up in the LL_PLL_ConfigSystemClock_HSE HAL function that passes the "prediv" value from the PLL init struct to LL_RCC_PLL_ConfigDomain_SYS. As far as I can see it does not handle the shifting to the right position or any parsing of the "prediv" value.

But since this config option was removed on purpose I am wondering if I am doing something wrong here. What is the intended way of configuring this option?

Can you please let me know if anyone got this working?

Thanks a lot for your help!

Best regards,

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