Date   

Final Reminder: CFP -- Zephyr Developer Summit 2021

Brett Preston
 

Members of the Zephyr Community,

A final reminder that the Call for Papers for the Zephyr Developer Summit closes tomorrow (Tuesday, April 20):

Look for schedule announcement and registration on May 5.

Thank you,


Brett


On Wed, Apr 14, 2021 at 10:00 AM Brett Preston <bpreston@...> wrote:
Members of the Zephyr Community,

A reminder of the Call for Papers that remains open until Tuesday, April 20:

The Zephyr Developer Summit has been scheduled for Tuesday, June 8 - Thursday, June 10, 2021

This free virtual event will feature two tracks:

Track A: Mini-conference (each will be 120 minutes in length)
  • This track is designed to let the organizer(s) focus on discussing an open topic with the other key participants.  A successful mini-conference outlines a problem and provides sufficient background so participants can engage in effective discussion.   Examples where this style is used:  Linux Plumbers, Conference Fishbowl Sessions, extended BOF etc.  Goal here is to have an effective discussion session and make progress on an outstanding problem.
  • Some possible topic areas could include:
    • Firmware
    • Modules
    • Networking Stack
    • Power Management
    • Toolchain
    • Topics identified in 2020 developer survey
Track B: Presentations. (choice of 30 or 60 minutes in length or lighting talks)
  • This is designed for sharing knowledge and providing context for other discussions.
  • Some possible topic ideas include:
    • How is Zephyr being used in products
    • Demos of tools working with Zephyr
    • Overview of proposed technologies for inclusion
    • Summary of what’s happening in subsystems
    • Updates on west, modules, runtimes, etc.
    • Security & Safety team updates
    • Test infrastructure Improvements
    • BOF topics
    • Lightning talk on something cool in Zephyr you want to share

Other Key Dates
  • May 5 - Schedule announcement
  • May 5 - Registration opens

Thank you!


Brett


On Wed, Apr 7, 2021 at 4:16 PM Brett Preston <bpreston@...> wrote:
Members of the Zephyr Community,

The inaugural Zephyr Developer Summit has been scheduled for Tuesday, June 8 - Thursday, June 10, 2021.

Furthermore, the Call for Papers is Now Openhttps://forms.gle/i637wnnBp9ahrnc37 (closes April 20).

This free virtual event will feature two tracks:

Track A: Mini-conference (each will be 120 minutes in length)
  • This track is designed to let the organizer(s) focus on discussing an open topic with the other key participants.  A successful mini-conference outlines a problem and provides sufficient background so participants can engage in effective discussion.   Examples where this style is used:  Linux Plumbers, Conference Fishbowl Sessions, extended BOF etc.  Goal here is to have an effective discussion session and make progress on an outstanding problem.
  • Some possible topic areas could include:
    • Firmware
    • Modules
    • Networking Stack
    • Power Management
    • Toolchain
    • Topics identified in 2020 developer survey
Track B: Presentations. (choice of 30 or 60 minutes in length or lighting talks)
  • This is designed for sharing knowledge and providing context for other discussions.
  • Some possible topic ideas include:
    • How is Zephyr being used in products
    • Demos of tools working with Zephyr
    • Overview of proposed technologies for inclusion
    • Summary of what’s happening in subsystems
    • Updates on west, modules, runtimes, etc.
    • Security & Safety team updates
    • Test infrastructure Improvements
    • BOF topics
    • Lightning talk on something cool in Zephyr you want to share

Other Key Dates
  • May 5 - Schedule announcement
  • May 5 - Registration opens

Thank you,


Brett

--
Brett Preston
Sr. Program Manager
The Linux Foundation
+1 (971) 303-9030



--
Brett Preston
Sr. Program Manager
The Linux Foundation
+1 (971) 303-9030



--
Brett Preston
Sr. Program Manager
The Linux Foundation
+1 (971) 303-9030


HC-SR04 connection to particle argon #nrf52480

Smitha Ratnam <s.ratnam@...>
 

I need to connect the HC-SR04 ultrasonic sensor to the particle argon board and use it for distance measurement with Zephyr.
What is the device binding that needs to be done in zephyr for this?
Are there any zephyr samples that can help?

Thanks and regards,
Smitha.


HC-SR04 connection to particle argon

s.ratnam@...
 

Hi,

I need to connect the HC-SR04 ultrasonic sensor to the particle argon board and use it for distance measurement with Zephyr.
What is the device binding that needs to be done in zephyr for this?
Are there any zephyr samples that can help?

Please advise.
Thanks and regards,
Smitha.


Re: STM32F107 clocks

Erwan Gouriou
 

Awesome, thanks for sharing Artie!


Le ven. 16 avr. 2021 à 15:11, Attie Grande <attie.grande@...> a écrit :
Hi Gunnar,

We got the PLL2 code into the STM32CubeF1 codebase a little while ago [1].
There are also some patches for adding this support into Zephyr, but I
need to revisit them / make a PR now that the PLL2 support was merged
into STM32CubeF1... [2][3][4].

I hope that helps!

Attie

 [1]: https://github.com/STMicroelectronics/STM32CubeF1/commit/f5aaa9b45492d70585ade1dac4d1e33d5531c171
 [2]: https://github.com/argentum-systems/zephyr/commit/6c167af50aeca2fc5f6e760de205807fda51c1c9
 [3]: https://github.com/argentum-systems/zephyr/commit/cb65e6da942f907b63f0711b57318839561264b6
 [4]: https://github.com/argentum-systems/zephyr/commit/da99de64bcf9cbb3dc8a2e1da2e0a4fb9f45258b


On Thu, 15 Apr 2021 at 14:29, Erwan Gouriou <erwan.gouriou@...> wrote:
>
> Hi Gunnar,
>
> Unfortunately, we miss code for PLL2 configuration as PLL input.
> Though, I'm adding Attie who investigated that point and may have code to get it working.
>
> BR
> Erwan
>
> On Thu, 15 Apr 2021 at 10:51, Gunnar Bråding <gunnar@...> wrote:
>>
>> Hi!
>>
>> I got a board with the crystal at 25MHz, and need to use the PLL2 as input to the system clock.
>> I just do not seem to understand the code enough to see how to set the prediv and multiplication for the PLL2
>> I can choose PLL2 as input to the PLL, and PLL as input to the system clock, but how do set the parameters for PLL2?
>>
>> Any pointers would be very much appreciated.
>>
>> Cheers,
>> — Gunnar
>>
>>
>>
>>


Re: STM32F107 clocks

Attie Grande <attie.grande@...>
 

Hi Gunnar,

We got the PLL2 code into the STM32CubeF1 codebase a little while ago [1].
There are also some patches for adding this support into Zephyr, but I
need to revisit them / make a PR now that the PLL2 support was merged
into STM32CubeF1... [2][3][4].

I hope that helps!

Attie

[1]: https://github.com/STMicroelectronics/STM32CubeF1/commit/f5aaa9b45492d70585ade1dac4d1e33d5531c171
[2]: https://github.com/argentum-systems/zephyr/commit/6c167af50aeca2fc5f6e760de205807fda51c1c9
[3]: https://github.com/argentum-systems/zephyr/commit/cb65e6da942f907b63f0711b57318839561264b6
[4]: https://github.com/argentum-systems/zephyr/commit/da99de64bcf9cbb3dc8a2e1da2e0a4fb9f45258b

On Thu, 15 Apr 2021 at 14:29, Erwan Gouriou <erwan.gouriou@linaro.org> wrote:

Hi Gunnar,

Unfortunately, we miss code for PLL2 configuration as PLL input.
Though, I'm adding Attie who investigated that point and may have code to get it working.

BR
Erwan

On Thu, 15 Apr 2021 at 10:51, Gunnar Bråding <gunnar@astrogator.se> wrote:

Hi!

I got a board with the crystal at 25MHz, and need to use the PLL2 as input to the system clock.
I just do not seem to understand the code enough to see how to set the prediv and multiplication for the PLL2
I can choose PLL2 as input to the PLL, and PLL as input to the system clock, but how do set the parameters for PLL2?

Any pointers would be very much appreciated.

Cheers,
— Gunnar




Re: STM32F107 clocks

Gunnar Bråding
 

Ahhh... Thanks! Then I don’t  need to feel too stupid for not understanding it. 😀

Cheers,
-- Gunnar


On 15 Apr 2021, at 15:29, Erwan Gouriou <erwan.gouriou@...> wrote:


Hi Gunnar,

Unfortunately, we miss code for PLL2 configuration as PLL input.
Though, I'm adding Attie who investigated that point and may have code to get it working.

BR
Erwan

On Thu, 15 Apr 2021 at 10:51, Gunnar Bråding <gunnar@...> wrote:
Hi!

I got a board with the crystal at 25MHz, and need to use the PLL2 as input to the system clock.
I just do not seem to understand the code enough to see how to set the prediv and multiplication for the PLL2
I can choose PLL2 as input to the PLL, and PLL as input to the system clock, but how do set the parameters for PLL2?

Any pointers would be very much appreciated.

Cheers,
— Gunnar





Re: STM32F107 clocks

Erwan Gouriou
 

Hi Gunnar,

Unfortunately, we miss code for PLL2 configuration as PLL input.
Though, I'm adding Attie who investigated that point and may have code to get it working.

BR
Erwan

On Thu, 15 Apr 2021 at 10:51, Gunnar Bråding <gunnar@...> wrote:
Hi!

I got a board with the crystal at 25MHz, and need to use the PLL2 as input to the system clock.
I just do not seem to understand the code enough to see how to set the prediv and multiplication for the PLL2
I can choose PLL2 as input to the PLL, and PLL as input to the system clock, but how do set the parameters for PLL2?

Any pointers would be very much appreciated.

Cheers,
— Gunnar





STM32F107 clocks

Gunnar Bråding
 

Hi!

I got a board with the crystal at 25MHz, and need to use the PLL2 as input to the system clock.
I just do not seem to understand the code enough to see how to set the prediv and multiplication for the PLL2
I can choose PLL2 as input to the PLL, and PLL as input to the system clock, but how do set the parameters for PLL2?

Any pointers would be very much appreciated.

Cheers,
— Gunnar


CFP Reminder -- Zephyr Developer Summit 2021

Brett Preston
 

Members of the Zephyr Community,

A reminder of the Call for Papers that remains open until Tuesday, April 20:

The Zephyr Developer Summit has been scheduled for Tuesday, June 8 - Thursday, June 10, 2021

This free virtual event will feature two tracks:

Track A: Mini-conference (each will be 120 minutes in length)
  • This track is designed to let the organizer(s) focus on discussing an open topic with the other key participants.  A successful mini-conference outlines a problem and provides sufficient background so participants can engage in effective discussion.   Examples where this style is used:  Linux Plumbers, Conference Fishbowl Sessions, extended BOF etc.  Goal here is to have an effective discussion session and make progress on an outstanding problem.
  • Some possible topic areas could include:
    • Firmware
    • Modules
    • Networking Stack
    • Power Management
    • Toolchain
    • Topics identified in 2020 developer survey
Track B: Presentations. (choice of 30 or 60 minutes in length or lighting talks)
  • This is designed for sharing knowledge and providing context for other discussions.
  • Some possible topic ideas include:
    • How is Zephyr being used in products
    • Demos of tools working with Zephyr
    • Overview of proposed technologies for inclusion
    • Summary of what’s happening in subsystems
    • Updates on west, modules, runtimes, etc.
    • Security & Safety team updates
    • Test infrastructure Improvements
    • BOF topics
    • Lightning talk on something cool in Zephyr you want to share

Other Key Dates
  • May 5 - Schedule announcement
  • May 5 - Registration opens

Thank you!


Brett


On Wed, Apr 7, 2021 at 4:16 PM Brett Preston <bpreston@...> wrote:
Members of the Zephyr Community,

The inaugural Zephyr Developer Summit has been scheduled for Tuesday, June 8 - Thursday, June 10, 2021.

Furthermore, the Call for Papers is Now Openhttps://forms.gle/i637wnnBp9ahrnc37 (closes April 20).

This free virtual event will feature two tracks:

Track A: Mini-conference (each will be 120 minutes in length)
  • This track is designed to let the organizer(s) focus on discussing an open topic with the other key participants.  A successful mini-conference outlines a problem and provides sufficient background so participants can engage in effective discussion.   Examples where this style is used:  Linux Plumbers, Conference Fishbowl Sessions, extended BOF etc.  Goal here is to have an effective discussion session and make progress on an outstanding problem.
  • Some possible topic areas could include:
    • Firmware
    • Modules
    • Networking Stack
    • Power Management
    • Toolchain
    • Topics identified in 2020 developer survey
Track B: Presentations. (choice of 30 or 60 minutes in length or lighting talks)
  • This is designed for sharing knowledge and providing context for other discussions.
  • Some possible topic ideas include:
    • How is Zephyr being used in products
    • Demos of tools working with Zephyr
    • Overview of proposed technologies for inclusion
    • Summary of what’s happening in subsystems
    • Updates on west, modules, runtimes, etc.
    • Security & Safety team updates
    • Test infrastructure Improvements
    • BOF topics
    • Lightning talk on something cool in Zephyr you want to share

Other Key Dates
  • May 5 - Schedule announcement
  • May 5 - Registration opens

Thank you,


Brett

--
Brett Preston
Sr. Program Manager
The Linux Foundation
+1 (971) 303-9030



--
Brett Preston
Sr. Program Manager
The Linux Foundation
+1 (971) 303-9030


Bluetooth support for Silicon Labs EFR32XX

chzfmx@163.com <chzfmx@...>
 

Hi ,
    My zephyr version is 2.5.0, and the board is EFR32_radio_brd4180a from Silicon Labs. 
    When I try to compile and run the Bluetooth routine (samples/blutooth/peripheral_hr), the serial port prints: "Bluetooth init failed (err -19)  , No HCI driver regsitered", and then I retrieved Issues#17005: https://github.com/zephyrproject-rtos/zephyr/issues/17005 . The conclusion is that it is almost difficult to provide Bluetooth support for Silicon Labs chips unless they provide library or register descriptions, so I would like to ask if there are any new developments or plans for the future.Thanks!
                                                                                                                                                                
                                                                                                                                            

chzfmx@...


brushless motor / servo driver in zephyr ?

popeye22202
 

Is there any brushless motor / servo drivers in zephyr ?

FYI, I've noticed various brushless software, such as :

http://vesc-project.com : ChibiOS based. Mostly motor code (originally
for skateboards), but added "VESCular6" servo code recently.

https://github.com/mjbots/moteus . mbed-os based. Mostly servo /
actuator code for robots, but he added motor code recently.

http://simplefoc.com : Arduino based.

I've been tinkering w/ a stm32 eval kit : P-NUCLEO-IHM001 with the ST
motor sdk, but I'd like to use Zephyr.

Thanks !


OS abstraction layer - CMSIS RTOS v1/v2 with Zephyr OS #osal #cmsis #api

Cap Able
 

Hello.

Are there any more specifics than provided in https://docs.zephyrproject.org/latest/guides/portability/index.html to be able use the CMSIS RTOS v2 (or V1) in Zephyr  OS? When enabled does it disable/replace the Zephyr OS kernel?

Also, is my understanding correct that the CMSIS would have to be treated as a Module (external project)? That this is ARM specific only? Is there a reference implementation that shows how the KConfig/yaml/CMakefiles are setup?


Re: Help using SystemView on an STM32 Nucleo board with re-flashed ST-Link #jlink #stm32

Raúl Sánchez Siles
 

  Hello:


  I remembered that Anas Nashif wrote a post about this subject:

https://www.planux.com/index.php/2018/08/21/tracing-zephyr-applications-with-segger-systemview/ 


  HTH, Regards,


El domingo, 4 de abril de 2021 3:15:14 (CEST) carlos.rodriguez via lists.zephyrproject.org escribió:

 

Hello:

 

I was wondering if the community could help me with using SystemView with Zephyr. 

 

When I connect to the board using JLink and then try to record with Systemview, I get a message telling me that the RTT control block was not detected.  If I force the call to SEGGER_SYSVIEW_Start() by either setting CONFIG_SEGGER_SYSTEMVIEW_BOOT_ENABLE=y or by putting it in my main function, what I get instead is a message to the effect that it can't find the SystemView buffer.

 

I believe I've been following the instructions correctly as outlined here:

 

https://docs.zephyrproject.org/2.4.0/guides/debugging/probes.html?highlight=segger.

 

and here

 

https://docs.zephyrproject.org/1.9.0/samples/subsys/debug/sysview/README.html

 

I am using Zephyr 2.4.9 with the 0.11.4 SDK on Ubuntu 20.4.

 

For the image, I am using the hello_world example and adding the following to the prj.conf file:

 

CONFIG_TRACING=y

CONFIG_SEGGER_SYSTEMVIEW=y

CONFIG_THREAD_NAME=y

CONFIG_USE_SEGGER_RTT=y

CONFIG_SEGGER_SYSTEMVIEW_BOOT_ENABLE=y

CONFIG_STDOUT_CONSOLE=y

 

It's interesting to note that JLink itself appears to connect just fine:

 

 Connecting to target via SWD

 Found SW-DP with ID 0x4BA01477

 STM32 (Protection Detection): Unexpected IDCODE DEV_ID 0x 461 found. Only checking the 1st flash bank for write protection.

 Found SW-DP with ID 0x4BA01477

 DPv0 detected

 Scanning AP map to find all available APs

 AP[1]: Stopped AP scan as end of AP map has been reached

 AP[0]: AHB-AP (IDR: 0x24770011)

 Iterating through AP map to find AHB-AP to use

 AP[0]: Core found

 AP[0]: AHB-AP ROM base: 0xE00FF000

 CPUID register: 0x410FC241. Implementer code: 0x41 (ARM)

 Found Cortex-M4 r0p1, Little endian.

 FPUnit: 6 code (BP) slots and 2 literal slots

 CoreSight components:

 ROMTbl[0] @ E00FF000

 ROMTbl[0][0]: E000E000, CID: B105E00D, PID: 000BB00C SCS-M7

 ROMTbl[0][1]: E0001000, CID: B105E00D, PID: 003BB002 DWT

 ROMTbl[0][2]: E0002000, CID: B105E00D, PID: 002BB003 FPB

 ROMTbl[0][3]: E0000000, CID: B105E00D, PID: 003BB001 ITM

 ROMTbl[0][4]: E0040000, CID: B105900D, PID: 000BB9A1 TPIU

 ROMTbl[0][5]: E0041000, CID: B105900D, PID: 000BB925 ETM

 Cortex-M4 identified.

 J-Link>

 

I am working on a Nucleo-L496ZG board, but the same thing happens on a Nucleo-F429Zi or a Nucleo-L4R5zi.  I am following the SEGGER instructions to flash the onboard ST-Links with JLink firmware, which appears to work fine.

 

Any help will be appreciated.

 

Best regards:

 

-Carlos Rodriguez.


--

Raúl Sánchez Siles


SW Engineer


K-LAGAN EID


Network forum agenda

Jukka Rissanen
 

Hi all,

There is a network forum meeting tomorrow Tue 6 Apr at 8AM PST / 17.00
CET.

Currently the agenda has one item:

* Network traffic monitoring (demo)

If there are any other network related topics you want to discuss,
please let me know.


Live Agenda/Minutes:
https://docs.google.com/document/d/1qFsOpvbyLzhflJbbv4Vl__497pKHDoUCy9hjAveyCX0/edit?usp=sharing

Shared Folder:
https://drive.google.com/drive/folders/1j6d0FLeOjiMil1Ellb59AsfHdzuWdAAc?usp=sharing

___________________________________________________________
Join Microsoft Teams Meeting (
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)


Cheers,
Jukka


Help using SystemView on an STM32 Nucleo board with re-flashed ST-Link #jlink #stm32

carlos.rodriguez@...
 

Hello:
 
I was wondering if the community could help me with using SystemView with Zephyr. 
 
When I connect to the board using JLink and then try to record with Systemview, I get a message telling me that the RTT control block was not detected.  If I force the call to SEGGER_SYSVIEW_Start() by either setting CONFIG_SEGGER_SYSTEMVIEW_BOOT_ENABLE=y or by putting it in my main function, what I get instead is a message to the effect that it can't find the SystemView buffer.
 
I believe I've been following the instructions correctly as outlined here:
 
https://docs.zephyrproject.org/2.4.0/guides/debugging/probes.html?highlight=segger.
 
and here
 
https://docs.zephyrproject.org/1.9.0/samples/subsys/debug/sysview/README.html
 
I am using Zephyr 2.4.9 with the 0.11.4 SDK on Ubuntu 20.4.
 
For the image, I am using the hello_world example and adding the following to the prj.conf file:
 
CONFIG_TRACING=y
CONFIG_SEGGER_SYSTEMVIEW=y
CONFIG_THREAD_NAME=y
CONFIG_USE_SEGGER_RTT=y
CONFIG_SEGGER_SYSTEMVIEW_BOOT_ENABLE=y
CONFIG_STDOUT_CONSOLE=y
 
It's interesting to note that JLink itself appears to connect just fine:
 
Connecting to target via SWD
Found SW-DP with ID 0x4BA01477
STM32 (Protection Detection): Unexpected IDCODE DEV_ID 0x 461 found. Only checking the 1st flash bank for write protection.
Found SW-DP with ID 0x4BA01477
DPv0 detected
Scanning AP map to find all available APs
AP[1]: Stopped AP scan as end of AP map has been reached
AP[0]: AHB-AP (IDR: 0x24770011)
Iterating through AP map to find AHB-AP to use
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xE00FF000
CPUID register: 0x410FC241. Implementer code: 0x41 (ARM)
Found Cortex-M4 r0p1, Little endian.
FPUnit: 6 code (BP) slots and 2 literal slots
CoreSight components:
ROMTbl[0] @ E00FF000
ROMTbl[0][0]: E000E000, CID: B105E00D, PID: 000BB00C SCS-M7
ROMTbl[0][1]: E0001000, CID: B105E00D, PID: 003BB002 DWT
ROMTbl[0][2]: E0002000, CID: B105E00D, PID: 002BB003 FPB
ROMTbl[0][3]: E0000000, CID: B105E00D, PID: 003BB001 ITM
ROMTbl[0][4]: E0040000, CID: B105900D, PID: 000BB9A1 TPIU
ROMTbl[0][5]: E0041000, CID: B105900D, PID: 000BB925 ETM
Cortex-M4 identified.
J-Link>
 
I am working on a Nucleo-L496ZG board, but the same thing happens on a Nucleo-F429Zi or a Nucleo-L4R5zi.  I am following the SEGGER instructions to flash the onboard ST-Links with JLink firmware, which appears to work fine.
 
Any help will be appreciated.
 
Best regards:
 
-Carlos Rodriguez.


Re: custom board #customboard #dts

Bolivar, Marti
 

Hi there,

The error message may have gotten lost in the rest of the output, but it
describes what went wrong, a stack trace where it went wrong, and how to
fix it:

"wbasser via lists.zephyrproject.org"
<wbasser=gmail.com@lists.zephyrproject.org> writes:

CMake Error at C:/zephyrproject/zephyr/boards/common/openocd-nrf5.board.cmake:13 (message):
Can't match nrf5 subfamily from BOARD name.  To fix, set CMake variable
OPENOCD_NRF5_SUBFAMILY.
Call Stack (most recent call first):
boards/arm/fuseboard/board.cmake:8 (include)
C:/zephyrproject/zephyr/cmake/app/boilerplate.cmake:622 (include)
C:/zephyrproject/zephyr/share/zephyr-package/cmake/ZephyrConfig.cmake:24 (include)
C:/zephyrproject/zephyr/share/zephyr-package/cmake/ZephyrConfig.cmake:35 (include_boilerplate)
CMakeLists.txt:10 (find_package)
Did you try setting the variable mentioned in the error in your
board.cmake before including openocd-nrf5.board.cmake?


Re: custom board #customboard #dts

Lawrence King
 

The Kconfig.defconfig doesn’t look right

 

config BOARD

              default "fuse board"

 

I think it should be “fuseboard” or maybe “fuse_board” but I didn’t test it. I looked at every other board name in the zephyr tree and none have a space in the default.

 

Lawrence King

Principal Developer

+1(416)627-7302

 

From: users@... <users@...> On Behalf Of wbasser@...
Sent: Wednesday, March 31, 2021 1:21 PM
To: users@...
Subject: [Zephyr-users] custom board #customboard #dts

 

Created a custom board file, based on the DTS for a sample board.  Changed the name of the file, and the references to the new board.  Attempting to build, I received this error.

C:\zephyrproject\zephyr>west build -p auto -b fuseboard c:/temp/fusetest

-- west build: making build dir C:\zephyrproject\zephyr\build pristine

-- west build: generating a build system

Including boilerplate (Zephyr base): C:/zephyrproject/zephyr/cmake/app/boilerplate.cmake

-- Application: C:/Temp/FuseTest

-- Zephyr version: 2.5.99 (C:/zephyrproject/zephyr)

-- Found Python3: C:/Python39/python.exe (found suitable exact version "3.9.2") found components: Interpreter

-- Found west (found suitable version "0.9.0", minimum required is "0.7.1")

-- Board: fuseboard

-- Cache files will be written to: C:/zephyrproject/zephyr/.cache

-- Found toolchain: gnuarmemb (c:/gnuarmemb)

-- Found BOARD.dts: C:/Temp/FuseTest/boards/arm/fuseboard/fuseboard.dts

-- Generated zephyr.dts: C:/zephyrproject/zephyr/build/zephyr/zephyr.dts

-- Generated devicetree_unfixed.h: C:/zephyrproject/zephyr/build/zephyr/include/generated/devicetree_unfixed.h

-- Generated device_extern.h: C:/zephyrproject/zephyr/build/zephyr/include/generated/device_extern.h

Parsing C:/zephyrproject/zephyr/Kconfig

Loaded configuration 'C:/Temp/FuseTest/boards/arm/fuseboard/fuseboard_defconfig'

Merged configuration 'C:/Temp/FuseTest/prj.conf'

Configuration saved to 'C:/zephyrproject/zephyr/build/zephyr/.config'

Kconfig header saved to 'C:/zephyrproject/zephyr/build/zephyr/include/generated/autoconf.h'

-- The C compiler identification is GNU 10.2.1

-- The CXX compiler identification is GNU 10.2.1

-- The ASM compiler identification is GNU

-- Found assembler: C:/gnuarmemb/bin/arm-none-eabi-gcc.exe

CMake Error at C:/zephyrproject/zephyr/boards/common/openocd-nrf5.board.cmake:13 (message):

  Can't match nrf5 subfamily from BOARD name.  To fix, set CMake variable

  OPENOCD_NRF5_SUBFAMILY.

Call Stack (most recent call first):

  boards/arm/fuseboard/board.cmake:8 (include)

  C:/zephyrproject/zephyr/cmake/app/boilerplate.cmake:622 (include)

  C:/zephyrproject/zephyr/share/zephyr-package/cmake/ZephyrConfig.cmake:24 (include)

  C:/zephyrproject/zephyr/share/zephyr-package/cmake/ZephyrConfig.cmake:35 (include_boilerplate)

  CMakeLists.txt:10 (find_package)

 

 

-- Configuring incomplete, errors occurred!

See also "C:/zephyrproject/zephyr/build/CMakeFiles/CMakeOutput.log".

See also "C:/zephyrproject/zephyr/build/CMakeFiles/CMakeError.log".

FATAL ERROR: command exited with status 1: 'C:\Program Files\CMake\bin\cmake.EXE' '-DWEST_PYTHON=c:\python39\python.exe' '-BC:\zephyrproject\zephyr\build' '-Sc:\temp\fusetest' -GNinja -DBOARD=fuseboard

I have had a successful attempt at this with a different family of processors with no problem.  

I have attached the project files for reference.

Any help would be appreciated.


custom board #customboard #dts

wbasser@...
 

Created a custom board file, based on the DTS for a sample board.  Changed the name of the file, and the references to the new board.  Attempting to build, I received this error.
C:\zephyrproject\zephyr>west build -p auto -b fuseboard c:/temp/fusetest
-- west build: making build dir C:\zephyrproject\zephyr\build pristine
-- west build: generating a build system
Including boilerplate (Zephyr base): C:/zephyrproject/zephyr/cmake/app/boilerplate.cmake
-- Application: C:/Temp/FuseTest
-- Zephyr version: 2.5.99 (C:/zephyrproject/zephyr)
-- Found Python3: C:/Python39/python.exe (found suitable exact version "3.9.2") found components: Interpreter
-- Found west (found suitable version "0.9.0", minimum required is "0.7.1")
-- Board: fuseboard
-- Cache files will be written to: C:/zephyrproject/zephyr/.cache
-- Found toolchain: gnuarmemb (c:/gnuarmemb)
-- Found BOARD.dts: C:/Temp/FuseTest/boards/arm/fuseboard/fuseboard.dts
-- Generated zephyr.dts: C:/zephyrproject/zephyr/build/zephyr/zephyr.dts
-- Generated devicetree_unfixed.h: C:/zephyrproject/zephyr/build/zephyr/include/generated/devicetree_unfixed.h
-- Generated device_extern.h: C:/zephyrproject/zephyr/build/zephyr/include/generated/device_extern.h
Parsing C:/zephyrproject/zephyr/Kconfig
Loaded configuration 'C:/Temp/FuseTest/boards/arm/fuseboard/fuseboard_defconfig'
Merged configuration 'C:/Temp/FuseTest/prj.conf'
Configuration saved to 'C:/zephyrproject/zephyr/build/zephyr/.config'
Kconfig header saved to 'C:/zephyrproject/zephyr/build/zephyr/include/generated/autoconf.h'
-- The C compiler identification is GNU 10.2.1
-- The CXX compiler identification is GNU 10.2.1
-- The ASM compiler identification is GNU
-- Found assembler: C:/gnuarmemb/bin/arm-none-eabi-gcc.exe
CMake Error at C:/zephyrproject/zephyr/boards/common/openocd-nrf5.board.cmake:13 (message):
  Can't match nrf5 subfamily from BOARD name.  To fix, set CMake variable
  OPENOCD_NRF5_SUBFAMILY.
Call Stack (most recent call first):
  boards/arm/fuseboard/board.cmake:8 (include)
  C:/zephyrproject/zephyr/cmake/app/boilerplate.cmake:622 (include)
  C:/zephyrproject/zephyr/share/zephyr-package/cmake/ZephyrConfig.cmake:24 (include)
  C:/zephyrproject/zephyr/share/zephyr-package/cmake/ZephyrConfig.cmake:35 (include_boilerplate)
  CMakeLists.txt:10 (find_package)
 
 
-- Configuring incomplete, errors occurred!
See also "C:/zephyrproject/zephyr/build/CMakeFiles/CMakeOutput.log".
See also "C:/zephyrproject/zephyr/build/CMakeFiles/CMakeError.log".
FATAL ERROR: command exited with status 1: 'C:\Program Files\CMake\bin\cmake.EXE' '-DWEST_PYTHON=c:\python39\python.exe' '-BC:\zephyrproject\zephyr\build' '-Sc:\temp\fusetest' -GNinja -DBOARD=fuseboard

I have had a successful attempt at this with a different family of processors with no problem.  

I have attached the project files for reference.

Any help would be appreciated.



Advertising/Scan ISO ticker nodes #ble

Carl Stehle
 

Hello,

When using CONFIG_BT_CTLR_ADV_ISO or CONFIG_BT_CTLR_SYNC_ISO, is it necessary to define ticker nodes in subsys/bluetooth/controller/ll_sw/ull.c:

#if defined(CONFIG_BT_CTLR_ADV_ISO)
#define BT_ADV_ISO_TICKER_NODES ((TICKER_ID_ADV_ISO_LAST) - \
                 (TICKER_ID_ADV_ISO_BASE) + 1)
#else
#define BT_ADV_ISO_TICKER_NODES 0
#endif

#if defined(CONFIG_BT_CTLR_SYNC_ISO)
#define BT_SCAN_SYNC_ISO_TICKER_NODES ((TICKER_ID_SCAN_SYNC_ISO_LAST) - \
                   (TICKER_ID_SCAN_SYNC_ISO_BASE) + 1)
#else
#define BT_SCAN_SYNC_ISO_TICKER_NODES 0
#endif

and add them to the definition:

#define TICKER_NODES              (TICKER_ID_ULL_BASE + \
                   BT_ADV_TICKER_NODES + \
                   BT_ADV_AUX_TICKER_NODES + \
                   BT_ADV_SYNC_TICKER_NODES + \
                   BT_ADV_ISO_TICKER_NODES + \
                   BT_SCAN_TICKER_NODES + \
                   BT_SCAN_AUX_TICKER_NODES + \
                   BT_SCAN_SYNC_TICKER_NODES + \
                   BT_SCAN_SYNC_ISO_TICKER_NODES + \
                   BT_CONN_TICKER_NODES + \
                   BT_CIG_TICKER_NODES + \
                   USER_TICKER_NODES + \
                   FLASH_TICKER_NODES)

Thank you,
Carl


Re: UART API Blocking TX

Tavish Naruka
 

Hi Jieng,

The uart_poll_out() API should be used for this, see https://docs.zephyrproject.org/latest/reference/peripherals/uart.html#c.uart_poll_out

Best,

Tavish

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