Date   

API meeting: agenda

Carles Cufi
 

Hi all,

*************************************************
We will be using Teams instead of Zoom:
https://teams.microsoft.com/l/meetup-join/19%3ameeting_YzYzZTAzNGItOWFiMS00MDBkLTkyYmMtNzljZjkwNDVlMThm%40thread.v2/0?context=%7b%22Tid%22%3a%22686ea1d3-bc2b-4c6f-a92c-d99c5c301635%22%2c%22Oid%22%3a%2262b63b80-05d3-4465-b5a0-f04e4e156f10%22%7d
*************************************************

Today's topics:

- PWM: Clarify expected behavior
- PR https://github.com/zephyrproject-rtos/zephyr/pull/25587

- API Change: Call UART_RX_RDY event after rx_disable()
- Issue https://github.com/zephyrproject-rtos/zephyr/issues/25317
- PR https://github.com/zephyrproject-rtos/zephyr/pull/25967

- API Change: Mesh: Add name parameter
- Issue https://github.com/zephyrproject-rtos/zephyr/issues/26037

Additional topics to review and close:

- QSPI flash drivers:
- Should we revisit the common QSPI API? https://github.com/zephyrproject-rtos/zephyr/pull/20069
- Should it be part of the current SPI API? https://github.com/zephyrproject-rtos/zephyr/issues/17902
- If not, should we try to unify the common functionality in the multiple QSPI flash drivers?
- https://github.com/zephyrproject-rtos/zephyr/pull/25806
- https://github.com/zephyrproject-rtos/zephyr/pull/25669

- SPI JEDEC runtime support
- PR https://github.com/zephyrproject-rtos/zephyr/pull/23658

- RTC API follow-up (if the relevant people are present and there is material for discussion)
- PR: https://github.com/zephyrproject-rtos/zephyr/pull/23526

Pending additional investigation:
- Documenting API behavior in Doxygen:
- Issue: https://github.com/zephyrproject-rtos/zephyr/issues/18970
- Issue: https://github.com/zephyrproject-rtos/zephyr/issues/21061

Additional items in the "Triage" column in the GitHub project may be discussed if time permits.
If you want an item included in the meeting, please add it to the GitHub project.

https://github.com/zephyrproject-rtos/zephyr/wiki/Zephyr-Committee-and-Working-Group-Meetings#zephyr-api-discussion
https://github.com/zephyrproject-rtos/zephyr/projects/18
https://docs.google.com/document/d/1lv-8B5QE2m4FjBcvfqAXFIgQfW5oz6306zJ7GIZIWCk/edit

Regards,

Carles


Re: Use different memory bank

Arvid Rosén
 

Great!

 

And yes, those are the old devicetree macros for the same thing. So you can keep the lines I sent as comments in the file until the time you upgrade (but maybe the numbers are different for 1060). Hopefully, we have a better solution for this by then, as the dts_fixup file is deprecated by now.

 

Cheers,

Arvid

 

From: Antoine Zen-Ruffinen <antoine@...>
Date: Monday, 8 June 2020 at 17:14
To: Arvid Rosén <arvid@...>, Henrik Brix Andersen <henrik@...>
Cc: "users@..." <users@...>
Subject: Re: [Zephyr-users] Use different memory bank

 

Thanks Arvid!

 

You solution worked! Thanks! But I had to modify it to work with my code base: 

 

#define ITCM_ADDR (DT_INST_0_NXP_IMX_ITCM_BASE_ADDRESS)

#define DTCM_ADDR (DT_INST_0_NXP_IMX_DTCM_BASE_ADDRESS)

 

I dont know why I had to use a different symbol name than you. Maybe because of Zehpyr version, we use currently 2.2.

 

Best regards,

 

Antoine


From: Arvid Rosén <arvid@...>
Sent: Monday, June 8, 2020 4:27:56 PM
To: Antoine Zen-Ruffinen; Henrik Brix Andersen
Cc: users@...
Subject: Re: [Zephyr-users] Use different memory bank

 

Hi Antoine,

 

We use CODE_DATA_RELOCATION on i.MX RT 1020. It is a bit of a hack though, but I added this to the dts_fixup.h for our board:

 

// Needed for CODE and DATA relocation

#define ITCM_ADDR (DT_N_S_soc_S_flexram_400b0000_S_itcm_0_REG_IDX_0_VAL_ADDRESS)

#define DTCM_ADDR (DT_N_S_soc_S_flexram_400b0000_S_dtcm_20000000_REG_IDX_0_VAL_ADDRESS)

#define OCRAM_ADDR (DT_N_S_soc_S_flexram_400b0000_S_ocram_20200000_REG_IDX_0_VAL_ADDRESS)

 

Obviously, this isn’t a good solution, but it does work for us at least.

 

It would be great with some input on howto solve this for real.

 

Best Regards,

Arvid

 

 

From: <users@...> on behalf of "Antoine Zen-Ruffinen via lists.zephyrproject.org" <antoine=riedonetworks.com@...>
Reply to: "antoine@..." <antoine@...>
Date: Monday, 8 June 2020 at 16:04
To: Henrik Brix Andersen <henrik@...>
Cc: "users@..." <users@...>
Subject: Re: [Zephyr-users] Use different memory bank

 

HI Brix,

 

Yes, I've tried that.  See in my first post:
 

> - How to specify that code should be relocated to ITCM while using CODE_DATA_RELOCATION ? I have tried "zephyr_code_relocate(ram_func.c ITCM)" but with no success.

 

As said, I was able to move come code to the SRAM but not to another RAM bank. Also I'm not sure that the BSP for the i.MXRT is doing it right. There is a few more memory region defined in the linker script in "soc/arm/nxp_imx/rt/linker.ld" and I think it is that that is printed at the end of the compilation. I think the related section are missing in the linker file. I don't know if the build system is expected to generate them from "zephyr_code_relocate() " and place them in the right memory region or if I need to do something extra. Also I like to have the code in ITCM memory (RAM) and data to DTCM memory from the same source file.


From: Henrik Brix Andersen <henrik@...>
Sent: Sunday, June 7, 2020 11:09:01 AM
To: Antoine Zen-Ruffinen
Cc: users@...
Subject: Re: [Zephyr-users] Use different memory bank

 

Hi Antoine,

Have you seen the instructions for code and data relocation in the Zephyr documentation?
https://docs.zephyrproject.org/latest/guides/code-relocation.html

Brix
-- 
Henrik Brix Andersen

> On 4 Jun 2020, at 17.32, Antoine Zen-Ruffinen <antoine@...> wrote:
>
> Hi,
>
> I have trouble getting full usage of the RAM on my SoC using zephyr and I might need a little help as I have not found the needed information in the doc. Here's the situation:
>
> I'm using Zephyr on the iMXRT1062 platform which is an Cortex-M7 with 3 separate non-contigus memory banks, from the datasheet (I's a little more complicated than that, but here I simplify):
>
> ITCM (Instruction Tight Coupled Memory) @ 0x0000'0000, size 128K
> DTCM (Data Tight Coupled Memory) @ 0x2000'0000, size 128K
> OCRAM (General RAM, slower) @ 0x2020'0000, size 768 K
>
> This setup is clearly defined in the .dts and the linker script in `zephyr/soc/arm/nxp_imx/rt/linker.ld`. When compiling an image, I get this same setup printed form the build system too (OCRAM is renamed SRAM by the build system, don't know why):
>
> ....
> [7/12] Linking C executable zephyr/zephyr_prebuilt.elf
> Memory region         Used Size  Region Size  %age Used
>             DTCM:          0 GB       128 KB      0.00%
>             ITCM:          0 GB       128 KB      0.00%
>            FLASH:      276524 B        16 MB      1.65%
>             SRAM:      114196 B       768 KB     14.52%
>         IDT_LIST:         344 B         2 KB     16.80%
> [12/12] Linking C executable zephyr/zephyr.elf
>
> As you can see all is placed in SRAM section. I can change and have everything linked to DTCM using KConfig option "CONFIG_DATA_DTCM", but then it's EVERTHING there . I've discovered that there is a macro `__dtcm_data_section` defined in `zephyr/include/linker/section_tags.h` that I thought it will place the variable in DTCM, but if I use it, I got the following error from the linker:
>
> /home/antoine/tools/SDKs/zephyr-sdk-0.11.1/arm-zephyr-eabi/bin/../lib/gcc/arm-zephyr-eabi/9.2.0/../../../../arm-zephyr-eabi/bin/ld: warning: orphan section `.dtcm_data' from `app/libapp.a(com_uart.c.obj)' being placed in section `.dtcm_data'
>
> My questions:
>
>  - How to use different non-contigus  memory region with Zephyr ?
>  - How can I specify what data should be placed on witch RAM bank ?
>  - How to specify that code should be relocated to ITCM while using CODE_DATA_RELOCATION ? I have tried "zephyr_code_relocate(ram_func.c ITCM)" but with no success.
>  - Can I place, for instance, all kernel code into ITCM with similar mechanism as "zephyr_code_relocate()" (ITCM  is faster than flash as the flash is external on this SoC)?
>
>
>
> Antoine Zen-Ruffinen
>
> Riedo Networks Ltd
> Route de la Fonderie 6, 1700 Fribourg, Switzerland
> Tel: +41 26 505 50 03, Fax: +41 26 505 50 01 www.riedonetworks.com
>


Re: Use different memory bank

Antoine Zen-Ruffinen
 

Thanks Arvid!


You solution worked! Thanks! But I had to modify it to work with my code base: 


#define ITCM_ADDR (DT_INST_0_NXP_IMX_ITCM_BASE_ADDRESS)
#define DTCM_ADDR (DT_INST_0_NXP_IMX_DTCM_BASE_ADDRESS)

I dont know why I had to use a different symbol name than you. Maybe because of Zehpyr version, we use currently 2.2.


Best regards,


Antoine


From: Arvid Rosén <arvid@...>
Sent: Monday, June 8, 2020 4:27:56 PM
To: Antoine Zen-Ruffinen; Henrik Brix Andersen
Cc: users@...
Subject: Re: [Zephyr-users] Use different memory bank
 

Hi Antoine,

 

We use CODE_DATA_RELOCATION on i.MX RT 1020. It is a bit of a hack though, but I added this to the dts_fixup.h for our board:

 

// Needed for CODE and DATA relocation

#define ITCM_ADDR (DT_N_S_soc_S_flexram_400b0000_S_itcm_0_REG_IDX_0_VAL_ADDRESS)

#define DTCM_ADDR (DT_N_S_soc_S_flexram_400b0000_S_dtcm_20000000_REG_IDX_0_VAL_ADDRESS)

#define OCRAM_ADDR (DT_N_S_soc_S_flexram_400b0000_S_ocram_20200000_REG_IDX_0_VAL_ADDRESS)

 

Obviously, this isn’t a good solution, but it does work for us at least.

 

It would be great with some input on howto solve this for real.

 

Best Regards,

Arvid

 

 

From: <users@...> on behalf of "Antoine Zen-Ruffinen via lists.zephyrproject.org" <antoine=riedonetworks.com@...>
Reply to: "antoine@..." <antoine@...>
Date: Monday, 8 June 2020 at 16:04
To: Henrik Brix Andersen <henrik@...>
Cc: "users@..." <users@...>
Subject: Re: [Zephyr-users] Use different memory bank

 

HI Brix,

 

Yes, I've tried that.  See in my first post:
 

> - How to specify that code should be relocated to ITCM while using CODE_DATA_RELOCATION ? I have tried "zephyr_code_relocate(ram_func.c ITCM)" but with no success.

 

As said, I was able to move come code to the SRAM but not to another RAM bank. Also I'm not sure that the BSP for the i.MXRT is doing it right. There is a few more memory region defined in the linker script in "soc/arm/nxp_imx/rt/linker.ld" and I think it is that that is printed at the end of the compilation. I think the related section are missing in the linker file. I don't know if the build system is expected to generate them from "zephyr_code_relocate() " and place them in the right memory region or if I need to do something extra. Also I like to have the code in ITCM memory (RAM) and data to DTCM memory from the same source file.


From: Henrik Brix Andersen <henrik@...>
Sent: Sunday, June 7, 2020 11:09:01 AM
To: Antoine Zen-Ruffinen
Cc: users@...
Subject: Re: [Zephyr-users] Use different memory bank

 

Hi Antoine,

Have you seen the instructions for code and data relocation in the Zephyr documentation?
https://docs.zephyrproject.org/latest/guides/code-relocation.html

Brix
-- 
Henrik Brix Andersen

> On 4 Jun 2020, at 17.32, Antoine Zen-Ruffinen <antoine@...> wrote:
>
> Hi,
>
> I have trouble getting full usage of the RAM on my SoC using zephyr and I might need a little help as I have not found the needed information in the doc. Here's the situation:
>
> I'm using Zephyr on the iMXRT1062 platform which is an Cortex-M7 with 3 separate non-contigus memory banks, from the datasheet (I's a little more complicated than that, but here I simplify):
>
> ITCM (Instruction Tight Coupled Memory) @ 0x0000'0000, size 128K
> DTCM (Data Tight Coupled Memory) @ 0x2000'0000, size 128K
> OCRAM (General RAM, slower) @ 0x2020'0000, size 768 K
>
> This setup is clearly defined in the .dts and the linker script in `zephyr/soc/arm/nxp_imx/rt/linker.ld`. When compiling an image, I get this same setup printed form the build system too (OCRAM is renamed SRAM by the build system, don't know why):
>
> ....
> [7/12] Linking C executable zephyr/zephyr_prebuilt.elf
> Memory region         Used Size  Region Size  %age Used
>             DTCM:          0 GB       128 KB      0.00%
>             ITCM:          0 GB       128 KB      0.00%
>            FLASH:      276524 B        16 MB      1.65%
>             SRAM:      114196 B       768 KB     14.52%
>         IDT_LIST:         344 B         2 KB     16.80%
> [12/12] Linking C executable zephyr/zephyr.elf
>
> As you can see all is placed in SRAM section. I can change and have everything linked to DTCM using KConfig option "CONFIG_DATA_DTCM", but then it's EVERTHING there . I've discovered that there is a macro `__dtcm_data_section` defined in `zephyr/include/linker/section_tags.h` that I thought it will place the variable in DTCM, but if I use it, I got the following error from the linker:
>
> /home/antoine/tools/SDKs/zephyr-sdk-0.11.1/arm-zephyr-eabi/bin/../lib/gcc/arm-zephyr-eabi/9.2.0/../../../../arm-zephyr-eabi/bin/ld: warning: orphan section `.dtcm_data' from `app/libapp.a(com_uart.c.obj)' being placed in section `.dtcm_data'
>
> My questions:
>
>  - How to use different non-contigus  memory region with Zephyr ?
>  - How can I specify what data should be placed on witch RAM bank ?
>  - How to specify that code should be relocated to ITCM while using CODE_DATA_RELOCATION ? I have tried "zephyr_code_relocate(ram_func.c ITCM)" but with no success.
>  - Can I place, for instance, all kernel code into ITCM with similar mechanism as "zephyr_code_relocate()" (ITCM  is faster than flash as the flash is external on this SoC)?
>
>
>
> Antoine Zen-Ruffinen
>
> Riedo Networks Ltd
> Route de la Fonderie 6, 1700 Fribourg, Switzerland
> Tel: +41 26 505 50 03, Fax: +41 26 505 50 01 www.riedonetworks.com
>


Re: Use different memory bank

Arvid Rosén
 

Hi Antoine,

 

We use CODE_DATA_RELOCATION on i.MX RT 1020. It is a bit of a hack though, but I added this to the dts_fixup.h for our board:

 

// Needed for CODE and DATA relocation

#define ITCM_ADDR (DT_N_S_soc_S_flexram_400b0000_S_itcm_0_REG_IDX_0_VAL_ADDRESS)

#define DTCM_ADDR (DT_N_S_soc_S_flexram_400b0000_S_dtcm_20000000_REG_IDX_0_VAL_ADDRESS)

#define OCRAM_ADDR (DT_N_S_soc_S_flexram_400b0000_S_ocram_20200000_REG_IDX_0_VAL_ADDRESS)

 

Obviously, this isn’t a good solution, but it does work for us at least.

 

It would be great with some input on howto solve this for real.

 

Best Regards,

Arvid

 

 

From: <users@...> on behalf of "Antoine Zen-Ruffinen via lists.zephyrproject.org" <antoine=riedonetworks.com@...>
Reply to: "antoine@..." <antoine@...>
Date: Monday, 8 June 2020 at 16:04
To: Henrik Brix Andersen <henrik@...>
Cc: "users@..." <users@...>
Subject: Re: [Zephyr-users] Use different memory bank

 

HI Brix,

 

Yes, I've tried that.  See in my first post:
 

> - How to specify that code should be relocated to ITCM while using CODE_DATA_RELOCATION ? I have tried "zephyr_code_relocate(ram_func.c ITCM)" but with no success.

 

As said, I was able to move come code to the SRAM but not to another RAM bank. Also I'm not sure that the BSP for the i.MXRT is doing it right. There is a few more memory region defined in the linker script in "soc/arm/nxp_imx/rt/linker.ld" and I think it is that that is printed at the end of the compilation. I think the related section are missing in the linker file. I don't know if the build system is expected to generate them from "zephyr_code_relocate() " and place them in the right memory region or if I need to do something extra. Also I like to have the code in ITCM memory (RAM) and data to DTCM memory from the same source file.


From: Henrik Brix Andersen <henrik@...>
Sent: Sunday, June 7, 2020 11:09:01 AM
To: Antoine Zen-Ruffinen
Cc: users@...
Subject: Re: [Zephyr-users] Use different memory bank

 

Hi Antoine,

Have you seen the instructions for code and data relocation in the Zephyr documentation?
https://docs.zephyrproject.org/latest/guides/code-relocation.html

Brix
-- 
Henrik Brix Andersen

> On 4 Jun 2020, at 17.32, Antoine Zen-Ruffinen <antoine@...> wrote:
>
> Hi,
>
> I have trouble getting full usage of the RAM on my SoC using zephyr and I might need a little help as I have not found the needed information in the doc. Here's the situation:
>
> I'm using Zephyr on the iMXRT1062 platform which is an Cortex-M7 with 3 separate non-contigus memory banks, from the datasheet (I's a little more complicated than that, but here I simplify):
>
> ITCM (Instruction Tight Coupled Memory) @ 0x0000'0000, size 128K
> DTCM (Data Tight Coupled Memory) @ 0x2000'0000, size 128K
> OCRAM (General RAM, slower) @ 0x2020'0000, size 768 K
>
> This setup is clearly defined in the .dts and the linker script in `zephyr/soc/arm/nxp_imx/rt/linker.ld`. When compiling an image, I get this same setup printed form the build system too (OCRAM is renamed SRAM by the build system, don't know why):
>
> ....
> [7/12] Linking C executable zephyr/zephyr_prebuilt.elf
> Memory region         Used Size  Region Size  %age Used
>             DTCM:          0 GB       128 KB      0.00%
>             ITCM:          0 GB       128 KB      0.00%
>            FLASH:      276524 B        16 MB      1.65%
>             SRAM:      114196 B       768 KB     14.52%
>         IDT_LIST:         344 B         2 KB     16.80%
> [12/12] Linking C executable zephyr/zephyr.elf
>
> As you can see all is placed in SRAM section. I can change and have everything linked to DTCM using KConfig option "CONFIG_DATA_DTCM", but then it's EVERTHING there . I've discovered that there is a macro `__dtcm_data_section` defined in `zephyr/include/linker/section_tags.h` that I thought it will place the variable in DTCM, but if I use it, I got the following error from the linker:
>
> /home/antoine/tools/SDKs/zephyr-sdk-0.11.1/arm-zephyr-eabi/bin/../lib/gcc/arm-zephyr-eabi/9.2.0/../../../../arm-zephyr-eabi/bin/ld: warning: orphan section `.dtcm_data' from `app/libapp.a(com_uart.c.obj)' being placed in section `.dtcm_data'
>
> My questions:
>
>  - How to use different non-contigus  memory region with Zephyr ?
>  - How can I specify what data should be placed on witch RAM bank ?
>  - How to specify that code should be relocated to ITCM while using CODE_DATA_RELOCATION ? I have tried "zephyr_code_relocate(ram_func.c ITCM)" but with no success.
>  - Can I place, for instance, all kernel code into ITCM with similar mechanism as "zephyr_code_relocate()" (ITCM  is faster than flash as the flash is external on this SoC)?
>
>
>
> Antoine Zen-Ruffinen
>
> Riedo Networks Ltd
> Route de la Fonderie 6, 1700 Fribourg, Switzerland
> Tel: +41 26 505 50 03, Fax: +41 26 505 50 01 www.riedonetworks.com
>


Re: Use different memory bank

Antoine Zen-Ruffinen
 

HI Brix,


Yes, I've tried that.  See in my first post:
 

> - How to specify that code should be relocated to ITCM while using CODE_DATA_RELOCATION ? I have tried "zephyr_code_relocate(ram_func.c ITCM)" but with no success.


As said, I was able to move come code to the SRAM but not to another RAM bank. Also I'm not sure that the BSP for the i.MXRT is doing it right. There is a few more memory region defined in the linker script in "soc/arm/nxp_imx/rt/linker.ld" and I think it is that that is printed at the end of the compilation. I think the related section are missing in the linker file. I don't know if the build system is expected to generate them from "zephyr_code_relocate() " and place them in the right memory region or if I need to do something extra. Also I like to have the code in ITCM memory (RAM) and data to DTCM memory from the same source file.


From: Henrik Brix Andersen <henrik@...>
Sent: Sunday, June 7, 2020 11:09:01 AM
To: Antoine Zen-Ruffinen
Cc: users@...
Subject: Re: [Zephyr-users] Use different memory bank
 
Hi Antoine,

Have you seen the instructions for code and data relocation in the Zephyr documentation?
https://docs.zephyrproject.org/latest/guides/code-relocation.html

Brix
-- 
Henrik Brix Andersen

> On 4 Jun 2020, at 17.32, Antoine Zen-Ruffinen <antoine@...> wrote:
>
> Hi,
>
> I have trouble getting full usage of the RAM on my SoC using zephyr and I might need a little help as I have not found the needed information in the doc. Here's the situation:
>
> I'm using Zephyr on the iMXRT1062 platform which is an Cortex-M7 with 3 separate non-contigus memory banks, from the datasheet (I's a little more complicated than that, but here I simplify):
>
> ITCM (Instruction Tight Coupled Memory) @ 0x0000'0000, size 128K
> DTCM (Data Tight Coupled Memory) @ 0x2000'0000, size 128K
> OCRAM (General RAM, slower) @ 0x2020'0000, size 768 K
>
> This setup is clearly defined in the .dts and the linker script in `zephyr/soc/arm/nxp_imx/rt/linker.ld`. When compiling an image, I get this same setup printed form the build system too (OCRAM is renamed SRAM by the build system, don't know why):
>
> ....
> [7/12] Linking C executable zephyr/zephyr_prebuilt.elf
> Memory region         Used Size  Region Size  %age Used
>             DTCM:          0 GB       128 KB      0.00%
>             ITCM:          0 GB       128 KB      0.00%
>            FLASH:      276524 B        16 MB      1.65%
>             SRAM:      114196 B       768 KB     14.52%
>         IDT_LIST:         344 B         2 KB     16.80%
> [12/12] Linking C executable zephyr/zephyr.elf
>
> As you can see all is placed in SRAM section. I can change and have everything linked to DTCM using KConfig option "CONFIG_DATA_DTCM", but then it's EVERTHING there . I've discovered that there is a macro `__dtcm_data_section` defined in `zephyr/include/linker/section_tags.h` that I thought it will place the variable in DTCM, but if I use it, I got the following error from the linker:
>
> /home/antoine/tools/SDKs/zephyr-sdk-0.11.1/arm-zephyr-eabi/bin/../lib/gcc/arm-zephyr-eabi/9.2.0/../../../../arm-zephyr-eabi/bin/ld: warning: orphan section `.dtcm_data' from `app/libapp.a(com_uart.c.obj)' being placed in section `.dtcm_data'
>
> My questions:
>
>  - How to use different non-contigus  memory region with Zephyr ?
>  - How can I specify what data should be placed on witch RAM bank ?
>  - How to specify that code should be relocated to ITCM while using CODE_DATA_RELOCATION ? I have tried "zephyr_code_relocate(ram_func.c ITCM)" but with no success.
>  - Can I place, for instance, all kernel code into ITCM with similar mechanism as "zephyr_code_relocate()" (ITCM  is faster than flash as the flash is external on this SoC)?
>
>
>
> Antoine Zen-Ruffinen
>
> Riedo Networks Ltd
> Route de la Fonderie 6, 1700 Fribourg, Switzerland
> Tel: +41 26 505 50 03, Fax: +41 26 505 50 01 www.riedonetworks.com
>


Re: Use different memory bank

Henrik Brix Andersen
 

Hi Antoine,

Have you seen the instructions for code and data relocation in the Zephyr documentation?
https://docs.zephyrproject.org/latest/guides/code-relocation.html

Brix
--
Henrik Brix Andersen

On 4 Jun 2020, at 17.32, Antoine Zen-Ruffinen <antoine@riedonetworks.com> wrote:

Hi,

I have trouble getting full usage of the RAM on my SoC using zephyr and I might need a little help as I have not found the needed information in the doc. Here's the situation:

I'm using Zephyr on the iMXRT1062 platform which is an Cortex-M7 with 3 separate non-contigus memory banks, from the datasheet (I's a little more complicated than that, but here I simplify):

ITCM (Instruction Tight Coupled Memory) @ 0x0000'0000, size 128K
DTCM (Data Tight Coupled Memory) @ 0x2000'0000, size 128K
OCRAM (General RAM, slower) @ 0x2020'0000, size 768 K

This setup is clearly defined in the .dts and the linker script in `zephyr/soc/arm/nxp_imx/rt/linker.ld`. When compiling an image, I get this same setup printed form the build system too (OCRAM is renamed SRAM by the build system, don't know why):

....
[7/12] Linking C executable zephyr/zephyr_prebuilt.elf
Memory region Used Size Region Size %age Used
DTCM: 0 GB 128 KB 0.00%
ITCM: 0 GB 128 KB 0.00%
FLASH: 276524 B 16 MB 1.65%
SRAM: 114196 B 768 KB 14.52%
IDT_LIST: 344 B 2 KB 16.80%
[12/12] Linking C executable zephyr/zephyr.elf

As you can see all is placed in SRAM section. I can change and have everything linked to DTCM using KConfig option "CONFIG_DATA_DTCM", but then it's EVERTHING there . I've discovered that there is a macro `__dtcm_data_section` defined in `zephyr/include/linker/section_tags.h` that I thought it will place the variable in DTCM, but if I use it, I got the following error from the linker:

/home/antoine/tools/SDKs/zephyr-sdk-0.11.1/arm-zephyr-eabi/bin/../lib/gcc/arm-zephyr-eabi/9.2.0/../../../../arm-zephyr-eabi/bin/ld: warning: orphan section `.dtcm_data' from `app/libapp.a(com_uart.c.obj)' being placed in section `.dtcm_data'

My questions:

- How to use different non-contigus memory region with Zephyr ?
- How can I specify what data should be placed on witch RAM bank ?
- How to specify that code should be relocated to ITCM while using CODE_DATA_RELOCATION ? I have tried "zephyr_code_relocate(ram_func.c ITCM)" but with no success.
- Can I place, for instance, all kernel code into ITCM with similar mechanism as "zephyr_code_relocate()" (ITCM is faster than flash as the flash is external on this SoC)?



Antoine Zen-Ruffinen

Riedo Networks Ltd
Route de la Fonderie 6, 1700 Fribourg, Switzerland
Tel: +41 26 505 50 03, Fax: +41 26 505 50 01 www.riedonetworks.com


Seeed BLE Micro (nrf51822) hangs on k_msleep

Matias N. <matias@...>
 

Hi,
I'm starting a project based on the BLE Micro module from Seeedstudio. Since this "board" was not supported but the RedBear BLE nano board is the most similar one, I created a custom board directory for it using this as a template. I managed to flash the blinky sample to the module (using openocd and a ST-Link v2 clone device) and can also connect with gdb to debug. I have this module soldered to a custom PCB which features a LED and thus I set the correct LED GPIO in the dts file. I managed to control the LED but from my debugging it seems to hang when calling k_msleep(). When it hangs, if I pause the execution it appears to be right after the "wfi" instruction (i'm assuming the debugger breaks the sleep).

I'm not sure why this could be happening. My guess it is something to do with the clock configuration. The module features a 32.768hz crystal (just like the BLE Nano) but also a 16 MHz crystal (which I'm not sure is used or not by zephyr). I tried disabling tickless, but the behavior does not change.

As I'm new to zephyr I'm not quite sure what else to check. Googling for this problem I found old issues in GitHub relating to tickless mode, low-power, rtc, etc. But all seem to be merged/closed. I would appreciate any help in this.

Best,
Matias


Zephyr v2.3.0 released

Carles Cufi
 

Hi all,

We are pleased to announce the release of Zephyr RTOS version 2.3.0.

Major enhancements with this release include:

* A new Zephyr CMake package has been introduced, reducing the need for
environment variables

* A new Devicetree API, based on hierarchical macros, has been introduced. This
new API allows the C code to access virtually all nodes and properties in a
clean, organized fashion

* The kernel timeout API has been overhauled to be flexible and configurable,
with future support for features like 64-bit and absolute timeouts in mind

* A new k_heap/sys_heap heap allocator has been introduced, with much better
performance than the existing k_mem_pool/sys_mem_pool
Zephyr now integrates with the TF-M (Trusted Firmware M) PSA-compliant
framework

* The Bluetooth Low Energy Host now supports LE Advertising Extensions

* The CMSIS-DSP library is now included and integrated

The detailed release notes can be found here:
https://github.com/zephyrproject-rtos/zephyr/releases/tag/zephyr-v2.3.0

The next release, v2.4.0, is tentatively scheduled for September 25th 2020.

I would like to thank everybody who contributed to this release, be it with code, feedback or documentation.

Thanks,

Carles


Re: Zephyr "West" Issue

Kumar Gala
 

On Jun 4, 2020, at 4:59 PM, jim slaughter <jim.slaughter@sage-micro.com> wrote:

Hello,

I am using Ubuntu and have been through the Getting Started Document and have arrived at point where you:
Run the installer, installing the SDK in ~/zephyr-sdk-0.11.3:

I have done the commands"
chmod +x zephyr-sdk-0.11.3-setup.run
./zephyr-sdk-0.11.3-setup.run -- -d ~/zephyr-sdk-0.11.3

I never saw where I specify the architecture "IBEX small 32-bit RISC-V CPU"

This is what I have in the sdk directory:
jws@DESKTOP-AJSFNLH:~$ ls -l zephyr-sdk-0.11.3
total 0
drwxr-xr-x 1 jws jws 512 May 16 10:24 aarch64-zephyr-elf
drwxr-xr-x 1 jws jws 512 May 16 11:22 arc-zephyr-elf
drwxr-xr-x 1 jws jws 512 May 16 11:37 arm-zephyr-eabi
drwxr-xr-x 1 jws jws 512 May 16 09:50 cmake
drwxr-xr-x 1 jws jws 512 Jun 4 16:34 info-zephyr-sdk-0.11.3
drwxr-xr-x 1 jws jws 512 May 16 10:38 nios2-zephyr-elf
drwxr-xr-x 1 jws jws 512 May 16 10:43 riscv64-zephyr-elf
-rw-r--r-- 1 jws jws 7 Jun 4 16:34 sdk_version
drwxr-xr-x 1 jws jws 512 May 16 10:36 sparc-zephyr-elf
drwxr-xr-x 1 jws jws 512 May 16 10:50 sysroots
drwxr-xr-x 1 jws jws 512 May 16 10:22 x86_64-zephyr-elf
drwxrwxr-x 1 jws jws 512 Jun 4 16:33 xtensa
jws@DESKTOP-AJSFNLH:~$

What did I miss?
How do I get the IBEX included?
Any help please!
Thanks.
We have a generic risc-v toolchain that support both 32 and 64-bit risc-v (riscv64-zephyr-elf). There isn’t a specific toolchain for IBEX.

- k


Zephyr "West" Issue

jim slaughter <jim.slaughter@...>
 

Hello,

I am using Ubuntu and have been through the Getting Started Document and have arrived  at point where you:
Run the installer, installing the SDK in ~/zephyr-sdk-0.11.3:  

I have done the commands"
chmod +x zephyr-sdk-0.11.3-setup.run
./zephyr-sdk-0.11.3-setup.run -- -d ~/zephyr-sdk-0.11.3
I never saw where I specify the architecture  "IBEX small 32-bit RISC-V CPU"

This is what I have in the sdk directory:
jws@DESKTOP-AJSFNLH:~$ ls -l zephyr-sdk-0.11.3
total 0
drwxr-xr-x 1 jws jws 512 May 16 10:24 aarch64-zephyr-elf
drwxr-xr-x 1 jws jws 512 May 16 11:22 arc-zephyr-elf
drwxr-xr-x 1 jws jws 512 May 16 11:37 arm-zephyr-eabi
drwxr-xr-x 1 jws jws 512 May 16 09:50 cmake
drwxr-xr-x 1 jws jws 512 Jun  4 16:34 info-zephyr-sdk-0.11.3
drwxr-xr-x 1 jws jws 512 May 16 10:38 nios2-zephyr-elf
drwxr-xr-x 1 jws jws 512 May 16 10:43 riscv64-zephyr-elf
-rw-r--r-- 1 jws jws   7 Jun  4 16:34 sdk_version
drwxr-xr-x 1 jws jws 512 May 16 10:36 sparc-zephyr-elf
drwxr-xr-x 1 jws jws 512 May 16 10:50 sysroots
drwxr-xr-x 1 jws jws 512 May 16 10:22 x86_64-zephyr-elf
drwxrwxr-x 1 jws jws 512 Jun  4 16:33 xtensa
jws@DESKTOP-AJSFNLH:~$

What did I miss?
How do I get the IBEX included?
Any help please!
Thanks.

--
Jim Slaughter


Re: Newbie question: How do I find out what's really there?

Carles Cufi
 

Hi Dave,

 

Most of the questions you ask are better answered by looking at the code directly. The level of detail you ask for is not reflected in the doc.

 

- Does the ethernet driver come from ST, or did someone write one that works?
Like most Zephyr drivers, it’s a shim on top of the vendor HAL:

https://github.com/zephyrproject-rtos/zephyr/blob/master/drivers/ethernet/eth_stm32_hal.c

 

- Does SPI support DMA transfers? CS?

I’d say yes based on light inspection:

https://github.com/zephyrproject-rtos/zephyr/blob/master/drivers/spi/spi_ll_stm32.c#L60


- What classes does USB driver support?

That one is easy:

https://github.com/zephyrproject-rtos/zephyr/tree/master/subsys/usb/class

 

  • HCI
  • CDC/ACM
  • MSD
  • DFU
  • Audio
  • HID
  • ECM/EEM/RNDIS


- There's a version of this chip with lots of security hardware - how would I use that to support HTTPS etc?

 

For that better ask Erwan, who is the STM32 maintainer.

 

Carles

 

From: users@... <users@...> On Behalf Of Dave Nadler via lists.zephyrproject.org
Sent: 04 June 2020 19:30
To: users@...
Subject: [Zephyr-users] Newbie question: How do I find out what's really there?

 

I'm a longtime FreeRTOS user (many shipping products) interested in Zephyr.
Why? Tired of the endless hassles and cost debugging and/or rewriting
crap drivers and/or FreeRTOS/LwIP integration provided by vendors (ST, Microchip, Silicon Labs, etc).

From that vantage, please tell me how I can find out,
what is *really* there?

For example: https://docs.zephyrproject.org/latest/boards/arm/nucleo_f429zi/doc/index.html

Great! But, uh...
- Does the ethernet driver come from ST, or did someone write one that works?
- Does SPI support DMA transfers? CS?
- What classes does USB driver support?
- There's a version of this chip with lots of security hardware - how would I use that to support HTTPS etc?

Its a serious question, and several others have shared the same question with me:
Where does one start, and how does one find out answers to such questions?

Any help much appreciated, Respectfully,
Thanks,
Best Regards, Dave

-- 
Dave Nadler, USA East Coast voice (978) 263-0097, drn@..., Skype 
 Dave.Nadler1


Newbie question: How do I find out what's really there?

Dave Nadler <drn@...>
 

I'm a longtime FreeRTOS user (many shipping products) interested in Zephyr.
Why? Tired of the endless hassles and cost debugging and/or rewriting
crap drivers and/or FreeRTOS/LwIP integration provided by vendors (ST, Microchip, Silicon Labs, etc).

From that vantage, please tell me how I can find out,
what is *really* there?

For example: https://docs.zephyrproject.org/latest/boards/arm/nucleo_f429zi/doc/index.html

Great! But, uh...
- Does the ethernet driver come from ST, or did someone write one that works?
- Does SPI support DMA transfers? CS?
- What classes does USB driver support?
- There's a version of this chip with lots of security hardware - how would I use that to support HTTPS etc?

Its a serious question, and several others have shared the same question with me:
Where does one start, and how does one find out answers to such questions?

Any help much appreciated, Respectfully,
Thanks,
Best Regards, Dave

-- 
Dave Nadler, USA East Coast voice (978) 263-0097, drn@..., Skype 
 Dave.Nadler1


Use different memory bank

Antoine Zen-Ruffinen
 

Hi,


I have trouble getting full usage of the RAM on my SoC using zephyr and I might need a little help as I have not found the needed information in the doc. Here's the situation:


I'm using Zephyr on the iMXRT1062 platform which is an Cortex-M7 with 3 separate non-contigus memory banks, from the datasheet (I's a little more complicated than that, but here I simplify):

ITCM (Instruction Tight Coupled Memory) @ 0x0000'0000, size 128K

DTCM (Data Tight Coupled Memory) @ 0x2000'0000, size 128K

OCRAM (General RAM, slower) @ 0x2020'0000, size 768 K


This setup is clearly defined in the .dts and the linker script in `zephyr/soc/arm/nxp_imx/rt/linker.ld`. When compiling an image, I get this same setup printed form the build system too (OCRAM is renamed SRAM by the build system, don't know why):


....

[7/12] Linking C executable zephyr/zephyr_prebuilt.elf
Memory region         Used Size  Region Size  %age Used
            DTCM:          0 GB       128 KB      0.00%
            ITCM:          0 GB       128 KB      0.00%
           FLASH:      276524 B        16 MB      1.65%
            SRAM:      114196 B       768 KB     14.52%
        IDT_LIST:         344 B         2 KB     16.80%
[12/12] Linking C executable zephyr/zephyr.elf

As you can see all is placed in SRAM section. I can change and have everything linked to DTCM using KConfig option "CONFIG_DATA_DTCM", but then it's EVERTHING there . I've discovered that there is a macro `__dtcm_data_section` defined in `zephyr/include/linker/section_tags.h` that I thought it will place the variable in DTCM, but if I use it, I got the following error from the linker:


/home/antoine/tools/SDKs/zephyr-sdk-0.11.1/arm-zephyr-eabi/bin/../lib/gcc/arm-zephyr-eabi/9.2.0/../../../../arm-zephyr-eabi/bin/ld: warning: orphan section `.dtcm_data' from `app/libapp.a(com_uart.c.obj)' being placed in section `.dtcm_data'


My questions: 


 - How to use different non-contigus  memory region with Zephyr ?

 - How can I specify what data should be placed on witch RAM bank ?

 - How to specify that code should be relocated to ITCM while using CODE_DATA_RELOCATION ? I have tried "zephyr_code_relocate(ram_func.c ITCM)" but with no success.

 - Can I place, for instance, all kernel code into ITCM with similar mechanism as "zephyr_code_relocate()" (ITCM  is faster than flash as the flash is external on this SoC)? 




Antoine Zen-Ruffinen

Riedo Networks Ltd
Route de la Fonderie 6, 1700 Fribourg, Switzerland
Tel: +41 26 505 50 03, Fax: +41 26 505 50 01 www.riedonetworks.com


Re: HAL architecture

Erwan Gouriou
 

Additionally to Carles's answer, let me point you to an on going PR that aims at implementing lp modes on stm32:

It only supports L4/WB series for now, but you can contact François in CC if you have some questions to adapt this to your use case.

Cheers

On Thu, 4 Jun 2020 at 16:58, Cufi, Carles <Carles.Cufi@...> wrote:

Hi Noëlle,

 

Thanks for the kind words.

You can use CMSIS, which is built-in with Zephyr, for WFI.

 

Simply use:

 

__WFI();

 

in your C code.

 

The definition is here:

https://github.com/zephyrproject-rtos/cmsis/blob/master/CMSIS/Core/Include/cmsis_gcc.h#L909

 

That said, are you sure you  need to invoke the WFI instruction manually? this is automatically done by Zephyr when the core can be powered down, for example:

https://github.com/zephyrproject-rtos/zephyr/blob/master/arch/arm/core/aarch32/cpu_idle.S#L101

 

Thanks,

 

Carles

 

From: users@... <users@...> On Behalf Of Noëlle Clement via lists.zephyrproject.org
Sent: 04 June 2020 15:09
To: users@...
Subject: [Zephyr-users] HAL architecture

 

Hi everyone!

 

First of all: thanks specifically to Carles Cufi for taking the time a few months ago to give very detailed answers to my questions on whether Zephyr would be a right choice for our device. Partially because of this we're going with Zephyr for now - at least for the upcoming phase where I'm going to develop a prototype!

 

The first step for this prototype is making sure that the OS actually supports the low power mode we need to still meet our battery life requirements. Some context:

- We use the STM32L151CC MCU

- We need to be able to request the WFI (wait_for_interrupt) instruction (we use that one right now)

- In our current (bare-metal) code we use CMSIS +  a separate library (STM32 Standard Peripheral Library), of which the latter actually includes functions for requesting low power modes (including WFI)

 

I'm trying to figure out whether this specific instruction is already part of the HAL of Zephyr for the STM32Lxx MCU's. However, I'm kind of getting lost in the code, since the abstraction seems to be dispersed over multiple locations. I've looked into the documentation of course, but wasn't able to find an answer for my specific question. 

 

It would help me tremendously if someone could point me in the right direction or give a summary of the architecture, so I can check whether it's already supported or can start with implementing it myself.

 

Quick note that I'm relatively new to this, so if you need more information to understand my question or help me, I'm happy to provide it!

 

All the best,

Noelle 

 


Re: HAL architecture

Carles Cufi
 

Hi Noëlle,

 

Thanks for the kind words.

You can use CMSIS, which is built-in with Zephyr, for WFI.

 

Simply use:

 

__WFI();

 

in your C code.

 

The definition is here:

https://github.com/zephyrproject-rtos/cmsis/blob/master/CMSIS/Core/Include/cmsis_gcc.h#L909

 

That said, are you sure you  need to invoke the WFI instruction manually? this is automatically done by Zephyr when the core can be powered down, for example:

https://github.com/zephyrproject-rtos/zephyr/blob/master/arch/arm/core/aarch32/cpu_idle.S#L101

 

Thanks,

 

Carles

 

From: users@... <users@...> On Behalf Of Noëlle Clement via lists.zephyrproject.org
Sent: 04 June 2020 15:09
To: users@...
Subject: [Zephyr-users] HAL architecture

 

Hi everyone!

 

First of all: thanks specifically to Carles Cufi for taking the time a few months ago to give very detailed answers to my questions on whether Zephyr would be a right choice for our device. Partially because of this we're going with Zephyr for now - at least for the upcoming phase where I'm going to develop a prototype!

 

The first step for this prototype is making sure that the OS actually supports the low power mode we need to still meet our battery life requirements. Some context:

- We use the STM32L151CC MCU

- We need to be able to request the WFI (wait_for_interrupt) instruction (we use that one right now)

- In our current (bare-metal) code we use CMSIS +  a separate library (STM32 Standard Peripheral Library), of which the latter actually includes functions for requesting low power modes (including WFI)

 

I'm trying to figure out whether this specific instruction is already part of the HAL of Zephyr for the STM32Lxx MCU's. However, I'm kind of getting lost in the code, since the abstraction seems to be dispersed over multiple locations. I've looked into the documentation of course, but wasn't able to find an answer for my specific question. 

 

It would help me tremendously if someone could point me in the right direction or give a summary of the architecture, so I can check whether it's already supported or can start with implementing it myself.

 

Quick note that I'm relatively new to this, so if you need more information to understand my question or help me, I'm happy to provide it!

 

All the best,

Noelle 

 


JSON

Xavier Naveira
 

Hello,

I am building an application on top of Zephyr that does communicate via MQTT to AWS IoT. I have been using the built in JSON library [1] to encode/parse the messages in json format.

Up until now all the structures that I needed to encode/parse to/from json have been static but I am beginning to encounter cases where some or several fields of a particular object are optional. For what I have seen in the documentation there doesn't seem to be support for optional fields in this library and I was wondering if anyone is using an external library for json and if yes what is the process they followed to incorporate it into their Zephyr app.

Thank you.

Xavier


HAL architecture

Noëlle Clement
 

Hi everyone!

First of all: thanks specifically to Carles Cufi for taking the time a few months ago to give very detailed answers to my questions on whether Zephyr would be a right choice for our device. Partially because of this we're going with Zephyr for now - at least for the upcoming phase where I'm going to develop a prototype!

The first step for this prototype is making sure that the OS actually supports the low power mode we need to still meet our battery life requirements. Some context:
- We use the STM32L151CC MCU
- We need to be able to request the WFI (wait_for_interrupt) instruction (we use that one right now)
- In our current (bare-metal) code we use CMSIS +  a separate library (STM32 Standard Peripheral Library), of which the latter actually includes functions for requesting low power modes (including WFI)

I'm trying to figure out whether this specific instruction is already part of the HAL of Zephyr for the STM32Lxx MCU's. However, I'm kind of getting lost in the code, since the abstraction seems to be dispersed over multiple locations. I've looked into the documentation of course, but wasn't able to find an answer for my specific question. 

It would help me tremendously if someone could point me in the right direction or give a summary of the architecture, so I can check whether it's already supported or can start with implementing it myself.

Quick note that I'm relatively new to this, so if you need more information to understand my question or help me, I'm happy to provide it!

All the best,
Noelle 


Re: Error in Getting Started Guide

Carles Cufi
 

Hi Jim,

 

Zephyr requires Python 3.6, you seem to be using Python 3.5.

 

Carles

 

 

From: users@... <users@...> On Behalf Of jim slaughter via lists.zephyrproject.org
Sent: 04 June 2020 00:33
To: users@...
Cc: jim slaughter <jim.slaughter@...>
Subject: [Zephyr-users] Error in Getting Started Guide

 

Hello,

 

I am new to Zephyr. Problem with Getting Started Guide, UBUNTU Tab

 

Get Zephyr and install Python dependencies

2. Get the Zephyr source code:  

1.  west init ~/zephyrproject

jws@DESKTOP-AJSFNLH:~$ west init ~/zephyrproject
Traceback (most recent call last):
  File "/home/jws/.local/bin/west", line 7, in <module>
    from west.app.main import main
  File "/home/jws/.local/lib/python3.5/site-packages/west/app/main.py", line 180
    log.die(f"file not found: {self.mle.filename}")                                              ^
SyntaxError: invalid syntax

 

Did I miss something in the instructions?

What is wrong?  Line 180

               # This should ordinarily only happen when the top
                # level west.yml is not found.
                log.die(f"file not found: {self.mle.filename}")

 

Thanks.

--

Jim Slaughter


Error in Getting Started Guide

jim slaughter <jim.slaughter@...>
 

Hello,

I am new to Zephyr. Problem with Getting Started Guide, UBUNTU Tab

Get Zephyr and install Python dependencies

2. Get the Zephyr source code:  
  1. west init ~/zephyrproject
jws@DESKTOP-AJSFNLH:~$ west init ~/zephyrproject
Traceback (most recent call last):
  File "/home/jws/.local/bin/west", line 7, in <module>
    from west.app.main import main
  File "/home/jws/.local/lib/python3.5/site-packages/west/app/main.py", line 180
    log.die(f"file not found: {self.mle.filename}")                                              ^
SyntaxError: invalid syntax

Did I miss something in the instructions?
What is wrong?  Line 180
               # This should ordinarily only happen when the top
                # level west.yml is not found.
                log.die(f"file not found: {self.mle.filename}")

Thanks.
--
Jim Slaughter


Zephyr 2.3.0-rc2 tagged

Carles Cufi
 

Hi all,

The second release candidate for Zephyr 2.3.0 has now been tagged (v2.3.0-rc2).

The current issue counts are:

- 1 high-priority bug
- 16 medium-priority bugs

The high-priority bug (#23364) has a PR (#25954), but a waiver to release without a fix for this particular issue has been requested, due to the invasiveness of the Pull Request and the risk of merging it this late in the release cycle. A note would be added to the release notes and a subsequent 2.3.1 would be released to address this issue.

During the days left until the release, I would encourage everybody to test thoroughly and file any issues found so that they can be fixed as quickly as possible. Additionally, there are still sections in the release notes that need filling, those can be tracked here:
https://github.com/zephyrproject-rtos/zephyr/issues/25869

The full release log can be found here:
https://github.com/zephyrproject-rtos/zephyr/releases/tag/v2.3.0-rc2

More details about Zephyr releases can found on the pages below:
https://docs.zephyrproject.org/latest/development_process/release_process.html
https://github.com/zephyrproject-rtos/zephyr/wiki/Program-Management

The final release remains scheduled for June 5th.

Thank you to everybody who contributed to this release so far!

Carles

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