TL;DR: - Upcoming device tree based pin configuration for STM32 based boards - Script generated, SoC package specific *-pinctrl.dtsi files are available in hal_stm32 modules - Each *.pcintrl.dtsi file

Thanks Brix. Helge, FYI, you might be interested in https://github.com/zephyrproject-rtos/zephyr/issues/27985 that will work around the issue for V2.4.0. BR Erwan

Hi Helge, Looking into it quickly, there has been no change in the init priorities on gpio or pinmux. board pinmux init: PRE_KERNEL_1 gpio init: POST_KERNEL So, what seems strange also is that it had

Additionally to Carles's answer, let me point you to an on going PR that aims at implementing lp modes on stm32: https://github.com/zephyrproject-rtos/zephyr/pull/19026 It only supports L4/WB series f

Hi, Can you check https://github.com/zephyrproject-rtos/hal_stm32#use-stm32cube-in-your-application and see if solving your issue ? Cheers Erwan

Hi Trevor, What is the error reported ? Erwan

You might just miss a "west update".

#stm32

Hi David, I'm not a SWO user myself but I'm suspecting a clock set up issue. On FreeRTOS, what was the clock configuration you were using ? Cheers

#debugging

Hi Zephyr users, In order to benefit from a wider range of user options [1], I'm proposing in PR 21791 to upgrade requirement for pyocd to version 0.24.0. Change should not have impact for most users,

Hi Pauli, If you are able to do what you want with Cube HAL then, to interface with zephyr, you just need to redefine the HAL callback (defined as weak in HAL drivr) in your zephyr application. You ca

#stm32

Hi Neo I'd advise you to have a look to STM32 clock control driver. It provides MCO support. It might not provide exactly the requested configuration, but at least it would be a working point that you

#stm32

Hi all, Optional property 'erase-block-size' is used to describe the minimum size of flash sector on which an erase operation could be applied. It is generated as a device tree generic define DT_FLASH

Hi Murad, Seems Cmake somehow convert you build path to a reserved Cmake string that trigger the issue. I'm not familiar with build on windows, but I'd suggest to work around your build path. Erwan

Hi Gustavo, Sorry, I'm not familiar with Dragino, nor J-Link, maybe Endre would know better, as he did the board port. Erwan

Hi Joseph, Which board are you using? Did you check that CAN driver is available for this board? Not sure it has been deployed for the whole STM32 family. Erwan

#stm32 #can

Hi Evan, You'll find the information in SoC's CMSIS file, available in STM32Cube SDK and under ext/hal/st/.../stm32f0/soc/ In that file, there's an enum with IRQ numbers. Erwan

Hi Evan, On most stm32, pinx from all gpios will share the same interrupt. For instance PA3, PC3 and PE3 share the same interrupt and hence same callback. Besides depending on series, you'll have furt

Hi Rob, clock_control_on won't help you for now as it is designed to enabled clock for subsystem (peripheral bus), and not to handle power management operations. The piece of code you need to (re)star

Hi Rob, When exiting stop mode PLL is disabled so you're running on HSI(or similar). This explain the change of clock speed after stop mode is exited. So you need to reconfigure and enable the PLL bef

Hi Stefan There is a PR opened on this exact topic: https://github.com/zephyrproject-rtos/zephyr/pull/8306 I suggest you have a look. Hih Cheers Erwan

#uart #flowcontrol #stm32