ESP32 Dual core - getting started


Lawrence King
 

Dear All:

 

I have started a new project based on ESP32.

 

To start I wrote boards files for the ESP32-CAM board  and defined a single LED as a peripheral. I was able to compile the blinky sample, flash it to the board and have it start up at board power on. Great!  I should mention that the ESP32-CAM board is a single core ESP32, and download is over the serial UART.

 

Now moving on to bigger and better things, I received a ESP32-WROVER-KIT board. This board has UART and JTAG debug on board and a dual-core CPU. I created a boards file(s) for this board (similar to the ESP32-CAM dts). I managed to get the esp variant of openOCD setup, it seems to download code to the board over JTAG correctly. Unfortunately when I reset the board it doesn’t run my Blinky code, it runs whatever was programmed in the board when I got it.

 

I think I have two issues, 1) which core is zephyr supposed to run on (cpu0 or cpu1), and 2) what address should the code be loaded to so that it will start at boot time?.

 

Here is the output of “west -v flash”:

 

-- west flash: using runner openocd

runners.openocd: /usr/local/bin/openocd -f board/esp32-wrover-kit-3.3v.cfg -c init -c targets -c 'reset halt' -c 'load_image /home/lawrence/workspace/cradle/build/zephyr/zephyr.elf' -c 'resume 0x00000000400807b4' -c shutdown

Open On-Chip Debugger  v0.10.0-esp32-20200526-33-gadc5c3ff-dirty (2020-10-09-17:36)

Licensed under GNU GPL v2

For bug reports, read

      http://openocd.org/doc/doxygen/bugs.html

Info : FreeRTOS creation

Info : FreeRTOS creation

Info : ftdi: if you experience problems at higher adapter clocks, try the command "ftdi_tdo_sample_edge falling"

Info : clock speed 20000 kHz

Info : JTAG tap: esp32.cpu0 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)

Info : JTAG tap: esp32.cpu1 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)

Info : esp32.cpu0: Debug controller was reset.

Info : esp32.cpu0: Core was reset.

Info : esp32.cpu1: Debug controller was reset.

Info : esp32.cpu1: Core was reset.

Info : Listening on port 3333 for gdb connections

    TargetName         Type       Endian TapName            State      

--  ------------------ ---------- ------ ------------------ ------------

0  esp32.cpu0         esp32      little esp32.cpu0         running

1* esp32.cpu1         esp32      little esp32.cpu1         running

 

Info : JTAG tap: esp32.cpu0 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)

Info : JTAG tap: esp32.cpu1 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)

Info : esp32.cpu0: Target halted, PC=0x400D5614, debug_reason=00000000

Info : Set GDB target to 'esp32.cpu0'

Info : esp32.cpu1: Target halted, PC=0x400D1AA6, debug_reason=00000000

Info : esp32.cpu0: Debug controller was reset.

Info : esp32.cpu0: Core was reset.

Info : esp32.cpu0: Target halted, PC=0x500000CF, debug_reason=00000000

Info : esp32.cpu0: Core was reset.

Info : esp32.cpu0: Target halted, PC=0x40000400, debug_reason=00000000

Info : esp32.cpu1: Debug controller was reset.

Info : esp32.cpu1: Core was reset.

Info : esp32.cpu1: Target halted, PC=0x40000400, debug_reason=00000000

14854 bytes written at address 0x40080000

920 bytes written at address 0x3ffb0000

downloaded 15774 bytes in 0.096819s (159.104 KiB/s)

 

shutdown command invoked

 

It looks like it wrote Zephyr to the chip (at address 0x40080000), and scribbled something at 0x3ffb0000. But when I restart the board the blinky code doesn’t run.

 

The serial terminal output shows it startes something else:

 

rst:0x1 (POWERON_RESET),boot:0x1e (SPI_FAST_FLASH_BOOT)

configsip: 0, SPIWP:0xee

clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00

mode:DIO, clock div:2

load:0x3fff0018,len:4

load:0x3fff001c,len:5984

ho 0 tail 12 room 4

load:0x40078000,len:0

load:0x40078000,len:15720

entry 0x4007901c

I (30) boot: ESP-IDF v3.1-dev-789-g0c58f11 2nd stage bootloader

I (30) boot: compile time 20:13:08

I (31) boot: Enabling RNG early entropy source...

I (36) qio_mode: Enabling default flash chip QIO

I (41) boot: SPI Speed      : 40MHz

I (45) boot: SPI Mode       : QIO

I (49) boot: SPI Flash Size : 2MB

I (54) boot: Partition Table:

I (57) boot: ## Label            Usage          Type ST Offset   Length

I (64) boot:  0 nvs              WiFi data        01 02 00009000 00006000

I (72) boot:  1 phy_init         RF data          01 01 0000f000 00001000

I (79) boot:  2 factory          factory app      00 00 00010000 00100000

I (87) boot: End of partition table

I (91) esp_image: segment 0: paddr=0x00010020 vaddr=0x3f400020 size=0x1d36c (119660) map

I (135) esp_image: segment 1: paddr=0x0002d394 vaddr=0x3ffb0000 size=0x025c0 (  9664) load

I (139) esp_image: segment 2: paddr=0x0002f95c vaddr=0x40080000 size=0x00400 (  1024) load

I (143) esp_image: segment 3: paddr=0x0002fd64 vaddr=0x40080400 size=0x002ac (   684) load

I (151) esp_image: segment 4: paddr=0x00030018 vaddr=0x400d0018 size=0x1a354 (107348) map

I (192) esp_image: segment 5: paddr=0x0004a374 vaddr=0x400806ac size=0x0d73c ( 55100) load

I (212) esp_image: segment 6: paddr=0x00057ab8 vaddr=0x400c0000 size=0x00000 (     0) load

I (221) boot: Loaded app from partition at offset 0x10000

I (221) boot: Disabling RNG early entropy source...

I (223) spiram: SPI RAM mode: flash 40m sram 40m

I (227) spiram: PSRAM initialized, cache is in low/high (2-core) mode.

I (234) cpu_start: Pro cpu up.

I (238) cpu_start: Starting app cpu, entry point is 0x4008111c

I (0) cpu_start: App cpu up.

I (1136) spiram: SPI SRAM memory test OK

I (1136) heap_init: Initializing. RAM available for dynamic allocation:

I (1137) heap_init: At 3FFAE6E0 len 00001920 (6 KiB): DRAM

I (1143) heap_init: At 3FFB3368 len 0002CC98 (179 KiB): DRAM

I (1149) heap_init: At 3FFE0440 len 00003BC0 (14 KiB): D/IRAM

I (1156) heap_init: At 3FFE4350 len 0001BCB0 (111 KiB): D/IRAM

I (1162) heap_init: At 4008DDE8 len 00012218 (72 KiB): IRAM

I (1168) cpu_start: Pro cpu start user code

I (1173) spiram: Adding pool of 4096K of external SPI memory to heap allocator

I (1181) spiram: Reserving pool of 32K of internal memory for DMA/internal allocations

I (196) cpu_start: Starting scheduler on PRO CPU.

I (0) cpu_start: Starting scheduler on APP CPU.

I (0) gpio: GPIO[0]| InputEn: 0| OutputEn: 1| OpenDrain: 0| Pullup: 1| Pulldown: 0| Intr:0

I (0) gpio: GPIO[2]| InputEn: 0| OutputEn: 1| OpenDrain: 0| Pullup: 1| Pulldown: 0| Intr:0

I (10) gpio: GPIO[4]| InputEn: 0| OutputEn: 1| OpenDrain: 0| Pullup: 1| Pulldown: 0| Intr:0

light init

LCD ID: 00000000

ILI9341 detected.

LCD ILI9341 initialization.

 

I suspect I set something up incorrectly, but what?

 

Lawrence King

Principal Developer

Connected Transport Market Unit

https://www.Irdeto.com

+1(416)627-7302

 

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