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Failure of CMD0 sending using STM32F769 + SPI2 for [samples/subsys/fs/fat_fs] #spi #fatfs


@yasokada
 

My environment:
Ubuntu 18.04 LTS
STM32L476 Nucleo_64 (hereafter STM32L476)
STM32F769 Discovery Kit (hereafter STM32F769)
Zephyr 2.1.0-rc1
Project: `samples/subsys/fs/fat_fs`
Logic Analyzer: Analog Discovery 2
 
### Difference
 
I have tested the sample project for microSD/MMC with FatFs (samples/subsys/fs/fat_fs).
 
The project works on some boards, but does not work on one board.
 
A. STM32L476 + SPI1 : O.K.
B. STM32L476 + SPI2 : O.K.
C. STM32F769 + SPI2 : Fail
 
### Logic capture for STM32L476
 
I have captured the SPI logic using Analog Discovery 2.
 
For STM32L476, the captured logics are shown below.





I can see:
 
1. 74 plus alpha clocks
2. MOSI: 0x40 0x00 0x00 0x00 0x00 0x94 0xFF 0xFF 0xFF
 
It works with STM32L476.
 
### Logic capture for STM32F769
 
I also have captured the SPI logic for STM32F769.





I saw:
 
1. 74 plus alpha clocks
2. MOSI: 0x20 0x00 0x00 0x00 0x00 0x4A ...

The step 2 is mistaken not CMD0 (0x40 0x00 0x00 0x00 0x00 0x94), possibly shifted sending.
 
### Possible cause of the failure
 
It seems that the 74 clocks do not end properly (ChipSelect did not go into low with margin).
This may cause the failure to send the CMD0 (0x40) command using STM32F769.
 
I will check how to solve this. But if anyone can suggest to fix this, it helps.
 
P.S. I will see on this after Jan. 3, 2020.
 


@yasokada
 

From what I checked:

- A. 74 clocks stop with a change in CS without sufficient delay
- B. CMD0 (0x40 0x00 0x00 0x00 0x00 0x94) fails to send 0x40... (instead send 0x20...)
- C. CMD0 fails to receive 0x01

I added `k_usleep(30); // usec` before sdhc_spi_set_cs(data, 0); in sdhc_spi_go_idle() of disk_access_spi_sdhc.c.
Then, the above A and B are solved.
However, I still have the problem of C.
This may be caused without sufficient delay after sending 0x94. I am checking how to add delay after 0x94.

I also checked the clock frequency.
- STM32L476: 312kHz
- STM32F768: 210kHz

I am not sure whether this difference in the frequency makes the failure and success of the process.


@yasokada
 

Instead of adding k_usleep(30),
I changed the SPI clock from 210kHz to 406kHz for STM32F769.

Then, the problems of A and B are gone.
Still I have the problem of C.
I receive 0x07 instead of 0x01.



From what I read throught the internet, the CRC for CMD is 0x95. But in Zephyr, the CRC is 0x94.
I wonder whether this difference cause some problem. However, for STM32L476, this works.

I will check further on this.